Design margin elimination in a near-threshold timing error masking-aware 32-bit ARM Cortex M0 in 40nm CMOS

Abstract

This paper presents a timing error masking-aware ARM Cortex M0 microcontroller system. Timing errors are detected through a timing error detection strategy, consisting of a soft edge flip-flop combined with a transition detector and an error latch. The time borrowing realized through soft edge flip-flops allows data to propagate after the clock edge (timing error masking). Thus operation at the point-of-first-failure is possible, effectively eliminating any timing margin. At the same time, time borrowing events are flagged which prevents corrupting the system state and allows dynamic voltage scaling. The error-aware microcontroller was implemented in a 40nm CMOS process and realizes ultra-low voltage operation down to 0.29V at 5MHz and 12.90pJ/cycle. 37% is energy overhead due to error detection. Minumum energy operation is achieved at 7.5MHz, 0.31V and 11.11pJ/cycle. A total of 75% energy is saved when comparing to a reference design without error detection running at slow-slow corner static timing analysis speed.