Timing error prediction based adaptive voltage scaling for dynamic variation tolerance

Abstract

There is always some conservative timing margin to ensure the chip to work properly under PVT variations during integrated circuit design time. The existence of the timing margin leads to a waste of power consumption. There are many adaptive techniques to monitor the on-chip timing error to reduce the timing error. In this paper, tunable replica paths which are a little more critical than the original critical paths have been designed and used to monitor the timing error with double-sampling monitors. In order to eliminate the timing margin as much as possible without causing real timing errors, the error prediction probability is analyzed to set the proper prediction alarm threshold for adaptive voltage scaling scheme. The whole scheme is used on a system-on-chip under TSMC 65nm CMOS process with a layout area of 2000μm∗1180μm, with the replica path and timing prediction mechanism costing only 2.7% area overhead. The post simulation results show that its power reduction is between 31.5% ∼ 42.2% compared with non-DVS scheme at 400MHz frequency, 25 °C, under different process corners (FF, FS, TT, SF and SS). The advantage of our proposed method lies in that it does not need to break the circuit architecture while offering decent power reduction by reducing the timing margin.