FDSOI MOSFETs Research Articles

Analysis of bipolar amplification due to heavy-ion irradiation in 45 nm FDSOI MOSFET with thin BOX and ground plane

Single event transient (SET) due to heavy-ion strike is one of the serious reliability issues when the MOSFET is scaled down to advanced technology nodes. SOI technology is more immune to SET than bulk technology due to its smaller collection volume and buried oxide (BOX). The device structure modification using thin BOX and ground plane (GP) doping will aid further scaling of SOI MOSFET. In this paper, the bipolar amplification due to heavy-ion strike is analysed for both thick BOX device and thin BOX device with GP in 45 nm SOI technology. The bipolar gain is reduced by optimizing GP doping. The effect of substrate bias and supply voltage scaling on the bipolar gain is also analysed. The replacement of thick BOX with thin BOX (without GP) reduces the bipolar gain by 3.2 times for LET = 0.2 MeV/(mg/cm2). The inclusion of a GP layer underneath the thin BOX reduces the bipolar gain further by 2.3 times. This lower bipolar amplification of thin BOX with GP device makes it to be less sensitive to the heavy-ion strike than the one with thick BOX.

Transient negative capacitance and charge trapping in FDSOI MOSFETs with ferroelectric HfYOX

Steep slope negative capacitance MOSFETs with HfYOx ferroelectric on FDSOI were experimentally demonstrated. An average SS of 30 mV/dec was achieved over 3 decades of drain current. The negative capacitance is believed to be a transient phenomenon because a strong polarization switching is needed for the steep slope. We found that the sub-thermal SS degrades with the cycling measurements, which is assumed to be caused by the trap charging in the ferroelectric oxide layer. The tradeoff between polarization and charge trapping is responsible for the subthreshold behavior of the device.

Linearity Distortion Assessment and Small-Signal Behavior of Nano-Scaled SOI MOSFET for Terahertz Applications

Fully-Depleted Silicon-on-Insulator (FD SOI) MOS technology has already been reported as a strong contender in nanoscale CMOS designs. This work presents the linearity-distortion assessment, small-signal and radio-frequency noise-behavior of dual-metal-insulated-gate (DMIG) source-engineered (SE) FD SOI MOSFET for terahertz (THz) applications. Here, linearity-distortion performance has been monitored on the basis of numerical calculations of transconductance and its higher-order derivatives along with the voltage-intercept points, and various parameters of intermodulation-distortion. This analysis also practices the guidelines of device design with least linearity-distortion in radio-frequency integrated-circuits based communication systems at 50 nm technology node. Further, the small-signal and RF noise-behavior have been examined on the basis of high-frequency scattering-parameters for the analysis of input/output reflection-coefficients (S11/S22), reverse/forward transmission-coefficients (S12/S21), Stern's-stability-factor (K), minimum noise-figure, noise-conductance and cross-correlation factor (<VN-in.VN-out*>). The analysed results affirm the ultimate reduction in reflection-coefficients and a significant increase in transmission-coefficients in case of DMIG FD SOI MOSFET at THz range as compared to existing MOS structures. Also, the analysis reveals the considerable reduction in various radio-frequency noise FOMs and thus represents the device efficacy in low-noise-amplifiers. All these studies have been carried out by performing numerical simulations over TCAD-ATLAS simulator from Silvaco along with quantum-mechanical-effect (QME) and Bohm-quantum-potential (BQP) models.

Design of High Speed and Low-Power Ring Oscillator Circuit in Recessed Source/Drain SOI Technology

In this paper, switching speed of CMOS inverter and Ring Oscillator is analyzed for the first time using Triple-Metal-Gate (TMG) Recessed-Source/Drain (Re-S/D) SOI MOSFET. Re-S/D SOI MOSFET has the capability to reduce the series resistance of the device due to the extended depth of source and drain into buried oxide layer. So the current drive capability of this device is improved which in turn improves the input/output switching in the inverter and ring oscillator. In this paper, transfer characteristics, delay and frequency is analyzed for inverter as well as for ring oscillator with TMG Re-S/D SOI MOSFET. DC and transient analysis such as transfer characteristics, noise margin, power dissipation, delay, and frequency is done for CMOS inverter and ring oscillator. Also, the Voltage Transfer Characteristic (VTC) has been compared with the available SMG and DMG structures of Re-S/D FD SOI MOSFET for the analysis switching behavior. This DC and transient simulation are performed using 2-dimensional numerical TCAD simulator ATLAS from Silvaco.

Transadmittance Efficiency Under NQS Operation in Asymmetric Double Gate FDSOI MOSFET

The state-of-the-art RF and millimeter-wave circuits design requires accurate prediction of the nonquasi-static (NQS) effects at high frequency for all levels of channel inversion. This paper provides a practical insight to help high-frequency performance assessment of ultrathin body and box fully depleted silicon-on-insulator MOSFETs through a powerful frequency normalization scheme. Frequency dependence of small signal characteristics derived from experimental S-parameters is analyzed and reveals that the transconductance efficiency ( ${g}_{\textsf {m}}/{I}_{\textsf {D}}$ ) concept, already adopted as a low-frequency analog figure-of-merit (FoM), can be generalized to high frequency, including under asymmetric operation. We report that the normalized frequency dependence of the generalized transadmittance efficiency ( ${y}_{\textsf {m}}/{I}_{\textsf {D}}$ ) FoM only depends on the mobility and inversion coefficient. In addition, this approach is also used to extract essential parameters such as the critical NQS frequency ${f}_{\textsf {NQS}}$ .

Threshold Voltage Model of Total Ionizing Irradiated Short-Channel FD-SOI MOSFETs With Gaussian Doping Profile

This paper investigates the effect of total dose radiation on the electrostatic potential distribution and the related short-channel effects (SCEs) of silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) devices with a vertical Gaussian doping profile. A new approximation of the 2-D potential function perpendicular to the channel for fully depleted SOI MOS field-effect transistors (FETs) is applied in the analytical threshold voltage model derivation. The impact of interface traps and oxide-trapped charge on the electrostatic potential profile, scaling, and SCEs are verified with TCAD simulations. The model agrees well with the experimental extractions of SCE in n-channel MOSFETs.

The total ionizing dose response of leading-edge FDSOI MOSFETs

In this paper, the total ionizing dose (TID) response of Ultra-Thin SOI (UTSOI) transistor is presented. TID experiments were performed on both NMOS and PMOS transistors under three different bias configurations (ON-state, OFF-state, TG-state). The results show that the OFF bias is relatively worse compared to other bias configurations for both NMOS and PMOS transistors. And the TID response variability caused by bias configuration during irradiation is small in UTSOI transistors. Besides this, the impact of back gate bias on TID response is also investigated. When a positive back bias is applied on NMOS transistor to achieve better performance, the threshold voltage degradation caused by TID becomes worse. While the negative back bias of PMOS transistor can lead to both better performance and higher TID tolerance. An explanation of back gate impact on front gate TID response is given with TCAD simulation.

A Study on Electrical Characterization of Surface Potential and Threshold Voltage for Nano Scale FDSOI MOSFET

In this paper the study of electrical characterization of Surface potential &amp; Vth threshold-voltage model is developed for FD SOI MOSFET. The threshold voltage is important parameter in device design. Scaling of device has positive impact on device performance. The various parameters like thickness of silicon film, oxide layer, drain to source voltage plays a key role in improvement of device performance. Surface potential explain the distribution of applied potential throughout the channel. We also analyzed the effect of threshold voltage with various electrical parameters.

Modeling of Induced Gate Thermal Noise Including Back-Bias Effect in FDSOI MOSFET

We present a charge-based compact model for induced gate thermal noise for a fully depleted silicon-on-insulator transistor. The model uses front- and back-gate charges as well as the respective mobilities for the development of analytical expression. The model is implemented in Verilog-A and validated with experimentally calibrated TCAD simulations. The model predicts the high-frequency behavior with good accuracy while capturing the back-bias dependence.

Kink effect in ultrathin FDSOI MOSFETs

Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling effect. For the first time, thanks to the availability of body contacts, the body potential is probed to evidence the impact of majority carrier accumulation and drain pulse duration on the kink effect onset.

Area efficient layout design of CMOS circuit for high-density ICs

ABSTRACTEfficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

Reliability improvement of a flexible FD-SOI MOSFET via heat management

Ultra-thin single-crystalline Si membrane transistors on a polymer substrate have drawn attention for flexible electronics applications. However, these devices accompany a reliability issue stemming from severe self-heating because of the inherent poor thermal conductivity of the polymer substrate. In the present study, under an operational condition of VG = 3 V and VD = 8 V, the temperature of the Si membrane transistor on the polymer substrate soared to about 64 °C immediately and remained consistently high. The excess heat generated from the active channel significantly degraded the device performance. However, the implementation of a silver heat spreading layer (HSL) between the active channel and the polymer substrate significantly alleviated the self-heating effect as the silver film rapidly spread the generated heat. The efficient heat spreading, monitored via a high resolution infrared thermal microscope, correlated well with the charge transfer characteristics of the device. These results may be helpful to realize high performance flexible devices using a silicon membrane.

(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI

1. Introduction Depleted body devices such as FinFETs and Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) MOSFETs have emerged as architectures of choice for technology nodes where conventional planar bulk devices do not provide enough immunity against short channel effects and variability. Offering unsurpassed electrostatic control of the channel, NanoWire FETs (NWFETs)-based architectures are considered as promising successors for future nodes. In all these depleted-body architectures, the control of active power is a strong requirement. Along with supply voltage scaling, it imposes design-level power management strategies, parasitic capacitance reduction and it calls for the use of high-mobility channel materials. For p-type channels, compressively strained silicon germanium alloys (SiGe) are attractive candidates. When depleted-body devices are fabricated on SOI, local germanium enrichment can convert Si to SiGe. This fabrication sequence starts with the growth of an epitaxial SiGe layer, followed by oxidation. During the latter, the surface of the SiGe layer is converted to silicon dioxide while Ge is segregated to the lower part of the stack, which gradually becomes more Ge-rich. This paper discusses the fabrication of SiGe channel for UTBBSOI MOSFETs, FinFETs and NWFETs. It reviews the key points associated to each architecture and critical aspects related to SiGe thermal budget, critical thickness, growth rate control and crystal quality. Results highlight the interest of NWFETs for future technology nodes. 2. SiGe channel UTBB FDSOI MOSFETs The Ge enrichment technique was initially developed for the planar FDSOI architecture and in that context, it was shown that high quality uniform SiGe films can be fabricated by alternating oxidizing and diffusion steps. For a SiGe/Si initial stack of given thickness and composition, the enrichment thermal budget needs to be significantly different when it is performed on SOI or on tensile SOI (sSOI). In the last case, the film initial tensile strain slows Ge diffusion (Fig. 1-a), which can lead to Ge pile up and defect formation if process temperature is too high with respect to the peak concentration (Fig. 1-b). Defect-free SiGe layers can be obtained on sSOI by using longer diffusion steps and reducing process temperature (Fig. 1-c). 3. SiGe-channel FinFET Although Ge enrichment can produce fully-strained layers, the patterning of SiGe blanket film into finite-dimension active areas yields elastic stress relaxation. This feature is particularly attractive for the fabrication of SiGe channel FinFETs where channel configuration results in longitudinal uniaxial compression, which is most favorable to hole transport. However, this processing sequence involves the elaboration of a thick blanket SiGe layer (through Ge enrichment and epitaxial thickening). Even with optimized processing, for a targeted Fin height (SiGe thickness) of 35 nm, significant crystal quality degradation is observed by X-Ray Reciprocal Space Mapping for {113} (RSM) when the Ge fraction approaches 50% (Fig. 2-a), in agreement with literature. To overcome this limit, Ge enrichment of already patterned Si Fins was investigated. This sequence relieves the limits set by SiGe critical thickness in the vertical direction, but it also constricts the pre-enrichment SiGe growth conditions. If SiGe growth rate is strongly dependent on crystal orientation, the final Fin profile is degraded (Fig. 2-b). In contrast, Fin profile can be maintained (Fig. 2-c) when uniform SiGe thickness can be achieved on Fin sidewalls (Fig. 2-d). RSM shows that Fins with up to 50% Ge fraction exhibit no significant relaxation (Fig. 2-e). This approach is expected to be most beneficial for tall Fins. 4. SiGe-channel NWFETs W-gate NWFETs were fabricated in a gate first scheme (Fig. 3-a). This configuration combines the respective benefits of SiGe channel FDSOI MOSFETs and FinFETs in terms of SiGe crystal stability [5] and uniaxial strain. With this and excellent electrostatic integrity, significant mobility gains are demonstrated down to a gate length of 14nm (Fig. 3-b), paving the way for future energy-efficient systems. 5. Acknowledgment Part of these results was obtained in a Joint Development Program between IBM, STMicroelectronics and LETI CEA. Figure 1

(Keynote) FD-SOI: The History from Early Transistors to Today

SOI technology was initiated in the mid 60’s by the quest for radiation-hard devices. Silicon on Sapphire (SOS) was the founder of the SOI family which later attracted many other members: epitaxial overgrowth (ELO), lamp or laser-induced melting and recrystallization (ZMR), wafer bonding and etch-back (BESOI), oxygen implantation (SIMOX), porous Si (FIPOS), etc. The coexistence of numerous options meant that none was really convincing as an industrial solution. The discovery of the Smart-Cut technology in early 90’s brought the necessary industrial momentum in terms of material quality, device performance and product adaptability to a variety of IC applications. The further development of Smart Cut Technology for ultra thin Si SOI in the mid 2000’s opened the door to a manufacturing-compatible planar fully-depleted CMOS IC platform, known today as FD-SOI. The basic mechanisms in fully depleted FD-SOI MOSFETs (interface coupling, back-biasing for threshold voltage adjustment, volume inversion, residual floating-body effects, etc.) have been understood early, when the thickness of Si film and buried dielectric was still in the micrometer range. Since then, these layers become two orders of magnitude thinner, revealing additional phenomena, for example reduced short-channel effects and size quantization. The concept of full depletion spread from FD-SOI to FinFETs and nanowire FETs simply because it is the unique solution for continuing the CMOS down-scaling. This paper reviews the milestones in FD-SOI history with the key technical steps, the strategic industrial decisions, the path to becoming a mass production qualified 22/28nm platform, the formation of the corresponding ecosystem, the early adopters and the markets driving its future growth. We will give a brief story of FD-SOI with insider experience and discuss its future prospects as the ultra low-power mixed signal & CMOS platform of the Internet of Things (IoT) era.SOI technology was initiated in the mid 60’s by the quest for radiation-hard devices. Silicon on Sapphire (SOS) was the founder of the SOI family which later attracted many other members: epitaxial overgrowth (ELO), lamp or laser-induced melting and recrystallization (ZMR), wafer bonding and etch-back (BESOI), oxygen implantation (SIMOX), porous Si (FIPOS), etc. The coexistence of numerous options meant that none was really convincing as an industrial solution. The discovery of the Smart-Cut technology in early 90’s brought the necessary industrial momentum in terms of material quality, device performance and product adaptability to a variety of IC applications. The further development of Smart Cut Technology for ultra thin Si SOI in the mid 2000’s opened the door to a manufacturing-compatible planar fully-depleted CMOS IC platform, known today as FD-SOI. The basic mechanisms in fully depleted FD-SOI MOSFETs (interface coupling, back-biasing for threshold voltage adjustment, volume inversion, residual floating-body effects, etc.) have been understood early, when the thickness of Si film and buried dielectric was still in the micrometer range. Since then, these layers become two orders of magnitude thinner, revealing additional phenomena, for example reduced short-channel effects and size quantization. The concept of full depletion spread from FD-SOI to FinFETs and nanowire FETs simply because it is the unique solution for continuing the CMOS down-scaling. This paper reviews the milestones in FD-SOI history with the key technical steps, the strategic industrial decisions, the path to becoming a mass production qualified 22/28nm platform, the formation of the corresponding ecosystem, the early adopters and the markets driving its future growth. We will give a brief story of FD-SOI with insider experience and discuss its future prospects as the ultra low-power mixed signal & CMOS platform of the Internet of Things (IoT) era.

Integration of Low Temperature SiGe:B Raised Sources and Drains in p-Type FDSOI Field Effect Transistors

In order to enable 3D sequential CoolCubeTM integration, low temperature epitaxy of raised sources and drains below 500°C is required. However, bad surface preparation and degradation of the epitaxial layer quality are then issues that need to be addressed. In this work, we first study different combinations of thermal, wet and dry surface preparation in order to find an optimum sequence. Then, we present for the first time the integration of SiGe:B raised sources and drains grown at 500°C in p-type FDSOI MOSFETs.

Study of Hot-Carrier-Induced Traps in Nanoscale UTBB FD-SOI MOSFETs by Low-Frequency Noise Measurements

The hot carrier (HC)-induced traps in nanoscale fully depleted ultrathin body and buried oxide nMOSFETs are investigated by low-frequency noise (LFN) measurements in the frequency and time domains. The measured noise spectra are composed of 1/f and Lorentzian-type components. The Lorentzian noise is due to either generation–recombination noise or random telegraph noise (RTN). Based on the LFN results, the effect of the HC stress on fully depleted silicon-on-insulator MOSFETs is investigated after short- and long-time stress. The capture and emission time constants responsible for the RTN noise were calculated as the average duration time of the high/low drain current state, respectively. Analysis of RTN traps detected in fresh and HC-stressed devices indicates that the RTN amplitude is uncorrelated to the trap time constants, i.e., the impact of the trap depth from the interface is masked by that of the trap location over the channel. The overall results lead to an analytical expression for the RTN amplitude, enabling to predict the RTN changes from the subthreshold to the above-threshold region.

On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two transistors connected in series with gates shortened, acting as a single device. The doping concentration of the two transistors in the structure is different, leading to higher threshold voltage of the transistor at the source side of the composite structure than that of the transistor at the drain side. By reducing the doping concentration level at the channel of the transistor at drain side of the composite structure, forcing it to work in saturation, part of the applied drain bias is absorbed and does not reach the transistor close to the source, which is the main responsible for the overall device characteristics. As a result, larger drain current level and transconductance are obtained in comparison to symmetric self-cascode (where both transistors present same doping level) apart from promoting output conductance reduction. The transconductance, output conductance, Early voltage, and intrinsic voltage gain are used as figures of merit to demonstrate and validate the advantages of the proposed structure. The influence of channel length and doping concentration are also evaluated. The A-SC configuration is fully compatible with any standard FD SOI MOSFET technology with multiple threshold voltages. A simulation analysis demonstrates the feasibility of the proposed asymmetric structure in a UTBB FD SOI technology.

(Plenary) Physical Insights on the Design of UTB Devices, Including FinFETs

A revolution in device design for nanoscale CMOS is now occurring because the conventional bulk-Si MOSFET can no longer be scaled due to channel-doping limitations. Two novel devices with undoped ultra-thin bodies (UTBs), the quasi-planar FinFET, on bulk Si or SOI, and the planar fully depleted (FD) SOI MOSFET, are now the prime candidates for nanoscale CMOS. This paper, based on our recently published textbook on UTB devices [1], overviews the unique physics of these new CMOS devices, and offers insights on their designs, scalabilities, and performance potentials. The characterization of the threshold voltage of the FinFET and the FD-SOI MOSFET is unique and generally complex, but generic, following from the application of Poisson's Equation and Gauss's Law in the undoped UTB. It simplifies for the long symmetrical double-gate (DG) FinFET (Vt ≈ ΦMSf + φc where φc ≈ 0.4V is the surface potential at the threshold condition), and, for the FD-SOI MOSFET, yields Vt(VGbS, ΦMSb) which shows how Vt can be varied via substrate bias and/or doping. Also, Vt is increased by energy quantization, dependent on UTB thickness (tSi, with tSi < 4nm being prohibitive) and transverse electric field, and it is decreased by short-channel effects (SCEs), dependent strongly on tSi. Regarding SCE control, the DG FinFET is superior to the FD-SOI MOSFET which requires substantially thinner tSi. The triple-gate (TG, with a fin-top gate) device is not much better than the DG device in this regard, nor does it offer much Ion improvement due to the prevalent bulk inversion in the undoped UTB. The SCE control is dramatically improved by a gate-source/drain underlap, defined by the source/drain lateral doping profile, that implies an effective channel length (Leff) longer than the gate length (Lg) for weak inversion, but Leff ≈ Lgfor strong inversion. Such optimal design is peculiar to undoped channels. The superior SCE control with FinFETs implies better scalability, and Intel Corp. has chosen [2] this device for its nanoscale CMOS. For vague reasons, it chose bulk Si for the substrate as opposed to SOI. Nonetheless, it appears that SOI will ultimately be needed (for Lg → <10nm), mainly because of unavoidable random variations in the high doping (PTS) density needed at the base of the fin to stop drain-source punch-through leakage. This leakage current is examined, in terms of the PTS doping density (~1018cm-3 is optimal), and variations in Vt and Iondue to the random PTS variations clearly imply problems in nanoscale bulk-Si FinFETs. Further, the PTS variations can undermine the control of the G-S/D underlap. The examination of the bulk-Si vs. SOI FinFET issue is concluded by noting a processing issue for FinFETs on SOI wafers, and suggesting that a local-SOI structure in bulk Si could be the ultimate solution. The physical insights overviewed herein imply a set of pragmatic FinFET design criteria that, we believe, can simplify the technology without undermining the CMOS performance much. They include the following: use an SOI structure (e.g., local in bulk Si); use an undoped UTB/channel with tSi > 4nm; use DG as opposed to TG; use no high-k dielectric (as implied by effects of strong bulk inversion); use one ~midgap metal gate for LP, and perhaps dual gates for HP; use optimal G-S/D underlap; use no channel strain (carrier mobilities can be high without it); and possibly use optimal S/D processing for Vtcontrol (and underlap). SRAM simulations demonstrate the viability of such pragmatic FinFET design.

High Mobility Materials on Insulator for Advanced Technology Nodes

Substrate Requirements & Product Roadmap Bulk silicon device technologies are reaching fundamental performance scaling limitations. To support Fully-Depleted SOI design introduction at 28nm node, SmartCut® technology has demonstrated in the past years its capability to deliver ultra-thin SOI (i.e ultra-thin silicon and ultra-thin buried oxide) substrates, in volume production mode with high quality and ultra-low roughness. [1, 2] These UTBOX (or UTBB) materials are routinely prepared with a typical SOI layer of 12nm thick controlled wafer to wafer and across the wafer at maximum +/- 0.5 nm. Buried Oxide layer can be thinned down to 10nm. Silicon on Insulator technology can also be adapted for other device architectures, such as FinFet on SOI. However, even if Silicon & Fully Depleted technology can support the electrostatic scaling down to 14nm node, material innovation is necessary for advanced technologies such as node 10nm and beyond. Strained-SOI material already demonstrates some of its substrate capability [3], performance benefit [4] and integration advantages [5] for 10nm FDSOI MOSFET. High mobility is also targeted using Germanium-rich materials, already known for extremely high hole mobility and low hole effective mass. [6] Thus SiGeOI material is included in product roadmap, as shown on Figure 1. This paper will report latest achievement in sSOI, GeOI, & SiGeOI materials preparation, developed to support technology nodes beyond 10nm. Substrate Preparation Fig. 2 shows typical SmartCut ® process, adapted for sSOI, GeOI & SiGeOI material preparation. It benefits of previous FDSOI developments optimizing buried oxide growth, ionic implant, bonding & splitting process steps for highly uniform thin layer transfer. It introduces engineered donor wafer including SiGe and/or strained-silicon Epi layers. Refresh process is also adjusted, to be able to re-use donor epitaxy, optimizing material cost & quality. During finishing process, specific steps including polishing, thermal treatment & cleanings are introduced to manage stress & germanium. GeOI Substrate Demonstration Fig. 3a shows TEM cross section of GeOI material, including 10nm Oxide capping, 60nm Ge layer and 150nm Buried Oxide. No crystal defect is observed by cross-sectional TEM. Using chemical etching for defect delineation, Threading Dislocation density, numbered from optical microscope view as on Fig. 3b, is estimated in E7 cm-2range. SiGe0.70OI Substrate Demonstration Germanium concentration on finished product, 70% on current development samples, is determined by donor epitaxy layer.To ensure tight thickness control, in addition to excellent Epitaxy uniformity & optimized SmartCut process, SiGeOI finishing process step implements the selective chemical etching instead of using the substantial polishing removal process as previously reported for GeOI substrate preparation.[7] As shown in Fig. 4a, it enables to reach the SiGe layer uniformity better than +/- 8% on 300mm substrates. Finished SiGeOI surface roughness is also characterized using 30x30 µm² AFM with a RMS value lower than 3 A (Fig. 4b).

Unusual gate coupling effect in extremely thin and short FDSOI MOSFETs

We investigated the characteristics of state-of-the-art FDSOI MOSFETs in a wide range of temperature by focusing on the effects of the back-gate bias, Si film thickness and channel length. High device performance and remarkably reduced short-channel effect with decreasing Si film thickness are achieved in ultra-thin film SOI devices. Systematic measurements reveal an unusual coupling effect resulting from the competition between front-gate, back-gate and temperature-dependent short-channel effect. Counter-intuitively, the impact of the back-gate bias can be smaller in 5nm than in 10nm thick MOSFETs, in particular in very short devices operated at 300K.