High Mobility Materials on Insulator for Advanced Technology Nodes

Abstract

Substrate Requirements & Product Roadmap Bulk silicon device technologies are reaching fundamental performance scaling limitations. To support Fully-Depleted SOI design introduction at 28nm node, SmartCut® technology has demonstrated in the past years its capability to deliver ultra-thin SOI (i.e ultra-thin silicon and ultra-thin buried oxide) substrates, in volume production mode with high quality and ultra-low roughness. [1, 2] These UTBOX (or UTBB) materials are routinely prepared with a typical SOI layer of 12nm thick controlled wafer to wafer and across the wafer at maximum +/- 0.5 nm. Buried Oxide layer can be thinned down to 10nm. Silicon on Insulator technology can also be adapted for other device architectures, such as FinFet on SOI. However, even if Silicon & Fully Depleted technology can support the electrostatic scaling down to 14nm node, material innovation is necessary for advanced technologies such as node 10nm and beyond. Strained-SOI material already demonstrates some of its substrate capability [3], performance benefit [4] and integration advantages [5] for 10nm FDSOI MOSFET. High mobility is also targeted using Germanium-rich materials, already known for extremely high hole mobility and low hole effective mass. [6] Thus SiGeOI material is included in product roadmap, as shown on Figure 1. This paper will report latest achievement in sSOI, GeOI, & SiGeOI materials preparation, developed to support technology nodes beyond 10nm. Substrate Preparation Fig. 2 shows typical SmartCut ® process, adapted for sSOI, GeOI & SiGeOI material preparation. It benefits of previous FDSOI developments optimizing buried oxide growth, ionic implant, bonding & splitting process steps for highly uniform thin layer transfer. It introduces engineered donor wafer including SiGe and/or strained-silicon Epi layers. Refresh process is also adjusted, to be able to re-use donor epitaxy, optimizing material cost & quality. During finishing process, specific steps including polishing, thermal treatment & cleanings are introduced to manage stress & germanium. GeOI Substrate Demonstration Fig. 3a shows TEM cross section of GeOI material, including 10nm Oxide capping, 60nm Ge layer and 150nm Buried Oxide. No crystal defect is observed by cross-sectional TEM. Using chemical etching for defect delineation, Threading Dislocation density, numbered from optical microscope view as on Fig. 3b, is estimated in E7 cm-2range. SiGe0.70OI Substrate Demonstration Germanium concentration on finished product, 70% on current development samples, is determined by donor epitaxy layer.To ensure tight thickness control, in addition to excellent Epitaxy uniformity & optimized SmartCut process, SiGeOI finishing process step implements the selective chemical etching instead of using the substantial polishing removal process as previously reported for GeOI substrate preparation.[7] As shown in Fig. 4a, it enables to reach the SiGe layer uniformity better than +/- 8% on 300mm substrates. Finished SiGeOI surface roughness is also characterized using 30x30 µm² AFM with a RMS value lower than 3 A (Fig. 4b).