FDSOI Devices Research Articles

Selective Epitaxy of Tensile, Highly Doped SiP for Planar NMOS FD-SOI Devices

The epitaxy of sources and drains is a critical enabler for enhanced transistor performances. In N-type MOS devices, selective SiP epitaxy can simultaneously yield (i) very high levels of electrically active dopants which is crucial for contact resistance minimization and (ii), tensile strain in Raised Sources and Drains (RSD) on each side of Si FD-SOI channels. This study present process solutions in order to benefit from large amounts of phosphorus in a silicon lattice and have thereby tensile strain, while maintaining excellent crystal quality, good surface morphology and a low electrical resistivity. We use here industrial precursors widely used in manufacturing, e.g. a [SiH2Cl2 + PH3 + HCl + H2] chemistry, for the selective deposition, in the 600°C-700°C range, of SiP in conventional epitaxy reactors. We achieved phosphorous concentrations as high as 4.6×10²¹ cm-3 (9.3%) in blanket SiP layers while preserving good crystal quality. In FD-SOI devices, we succeeded in having a selective process yielding rather smooth and free of defects Si:P films with 1.6×10²¹ cm-3(3.2%) of P.

Comparative Cryogenic Investigation of FD-SOI Devices with Doped Epitaxial and Metallic Source/Drain

Defects induced by the source/drain process have a significant impact on the scattering mechanism of PMOS at cryogenic temperatures. Here, the cryogenic characteristics of FD-SOI devices with heavily doped epitaxial source/drain (Epi FD-SOI devices) and metallic Schottky barrier source/drain (SB FD-SOI devices) were investigated from 300 K down to 6 K. The doping profile along the channel was analyzed by TCAD simulation analysis. Experimental comparison of transistor performance at cryogenic temperatures was carried out for these devices with gate lengths (L G ) of 100 nm and 40 nm. The I-V characteristics of the FD-SOI devices were measured with a liquid helium cooling environment. The cryogenic effect of the two types of devices on Key parameters including transconductance (G m ), field effect mobility (μ FE ), threshold voltage (V th ) and subthreshold slope (SS) were systematically analyzed. The doping distribution of the heavily doped epitaxial SiGe source/drain structure were subjected to more Coulomb scattering at cryogenic temperatures, whereas the doping distribution of the Schottky-barrier source/drain structure dictates that the device is mainly subjected to phonon scattering at cryogenic temperatures.

Total ionizing dose and single event effect response of 22 nm ultra-thin body and buried oxide fully depleted silicon-on-insulator technology

The test chip including transistors and Static Random Access Memory (SRAM) is proposed and fabricated by an advanced 22 nm Ultra-Thin Body and Buried Oxide Fully Depleted Silicon-on-Insulator (UTBB FD-SOI) technology. Experimental results of Co-60 irradiation and heavy ion experiments are presented. Total Ionizing Dose (TID) experiment results show that the threshold voltage shift of the transistor is about 100 mV when the dose is 500 krad(Si) and the SRAM irradiated to a dose of at least 300 krad(Si) can maintain its functionality, which means that 22 nm UTBB FD-SOI devices exhibit significantly improved total dose tolerance performance compared to the previous generation process. TID-induced threshold voltage shift in conventional-well nMOSFET can be mitigated by applying biasing to back-gate, while back-gate biasing is invalid for TID mitigation of the conventional-well pMOSFET. Heavy ion experimental results make known that 22 nm UTBB FD-SOI technology has contributions to Single Event Effect (SEE) hardness and the hardened SRAM has higher single event upset (SEU) tolerance and even SEU immunity. The research indicates that the circuits manufactured by 22 nm UTBB FD-SOI technology have great potential space applications in harsh radiation environments.

Random Telegraph Noise and Bias Temperature Instabilities statistical characterization of Ω-gate FDSOI devices at low voltages

Random Telegraph Noise (RTN) and Bias Temperature Instabilities (BTI) are two mechanisms that can significantly reduce the performance and reliability of integrated circuits. In scaled devices, both phenomena are stochastic, so that a statistical analysis is required to accurately evaluate their impact on a particular technology. This study presents such analysis in scaled FD-SOI devices under various gate and drain voltages, ranging from near-threshold to nominal conditions. The combined effect of RTN and BTI is also modeled in a defect-centric context, and the main impact of the different bias conditions is discussed.

Very Low Temperature Tensile and Selective Si:P Epitaxy for Advanced CMOS Devices

We demonstrate the feasibility of selectively growing highly doped and tensile-strained Si:P layers at temperatures 500°C or less on each side of advanced n-type MOS devices. To that end, we used a Cyclic Deposition Etch (CDE) strategy instead of a conventional “co-flow” approach fit for the high temperature (> 600°C) Selective Epitaxial Growth (SEG) of t-SiP films. A high order silicon precursor was used together with PH3 to benefit from high t-Si:P growth rates at 500°C and less. Selective etchings were performed with Cl2 as an etchant gas, as it yielded much higher etch rates than HCl. We first investigated the blanket growth of t-SiP on fullsheet Si wafers. 5 to 15 times higher higher growth rates than with standard precursors were obtained at low temperatures with our new HOS silicon precursor. We then investigated the etching efficiency of Cl2, with several tens of nanometers per minutes etch rates achieved at very low temperatures. Using a CDE strategy, we then probed phosphorus incorporation in blanket t-Si:P films on fullsheet wafers. High quality and smooth t-SiP layers with up to 5.4%, 4.3% and 5.8% of P and sheet resistances as low as 0.33, 0.27 and 0.21 mohm.cm were obtained at 500°C, 475°C and 450°C, respectively. We then tested our CDE SiP process for SEG, first on test structures then on each side of real FD-SOI devices, with smooth, high quality, tensile SiP layers grown at 500°C with 4.5% of P.

Prediction of electrical properties of FDSOI devices based on deep learning

Fully depleted Silicon on insulator technology (FDSOI) is proposed to solve the various non-ideal effects when the process size of integrated circuits is reduced to 45 nm. The research of traditional FDSOI devices is mostly based on simulation software, which requires a lot of calculation and takes a long time. In this paper, a deep learning (DL) based electrical characteristic prediction method for FDSOI devices is proposed. DL algorithm is used to train the simulation data and establish the relationship between the physical parameters and electrical characteristics of the device. The network structure used in the experiment has high prediction accuracy. The mean square error of electrical parameters and transfer characteristic curve is only 4.34 × 10–4 and 2.44 × 10–3 respectively. This method can quickly and accurately predict the electrical characteristics of FDSOI devices without microelectronic expertise. In addition, this method can be extended to study the effects of various physical variables on device performance, which provides a new research method for the field of microelectronics.

Performance of FDSOI double-gate dual-doped reconfigurable FETs

In this work, the electrical performance of a novel reprogrammable FDSOI device with dual-doping at source/drain and only two top gates is investigated through advanced 3D TCAD simulations. The static and dynamic operations are evaluated and compared with those of traditional Schottky barrier RFETs and standard 28 nm FDSOI MOS transistors under manufacturable geometries.

Characterization and Modeling of Quantum Dot Behavior in FDSOI Devices

A compact analytical model is proposed along with a parameter extraction methodology to accurately capture the steady-state (DC) sequential tunnelling current observed in the subthreshold region of the transfer IDS-VGS characteristics of MOSFETs at cryogenic temperatures. The model is shown to match measurements of p-MOSFETs and n-MOSFETs manufactured in a commercial 22nm FDSOI foundry technology, with reasonable accuracy across bias conditions and temperature (2 K -50 K). Furthermore, the extracted model parameters are used to analyze the impact of the gate and drain voltages and of layout geometry on the device characteristics.

1/f Noise responses of Ultra-Thin Body and Buried oxide FD-SOI PMOSFETs under total ionizing dose irradiation

This paper investigates the low frequency noise degradation of commercial Ultra-Thin Body and Buried oxide Fully Depleted Silicon on Insulator (UTBB FD-SOI) PMOSFETs are under Total Ionizing Dose (TID) irradiation. According to the experimental results, the 1/f noise of the conduction channel in studied transistors increases differently after irradiation. Based on the carrier number fluctuation (CNF) model with additional carrier mobility fluctuations (CMF), we expand the process of 1/f noise changes at the front and back gates in UTBB FD-SOI devices during TID irradiation. Moreover, the relationship between channel Width/Length ratio (W/L) and the 1/f noise normalized power spectral density at the front gate before and after TID irradiation is also discussed. The trend reducing W/L condition can alleviate 1/f noise degradation in transistors is consistent with the expended theory, which can be a practical reference to develop the UTBB FD-SOI radiation-hardening technology.

22nm FDSOI SRAM single event upset simulation analysis

This article uses Sentaurus TCAD to establish the 3D device model of NMOS and PMOS under the 22nm FDSOI process, and establishes the 3D model of the 22nm FDSOI SRAM cell through this model. This model is used to numerically simulate the single event upset LET threshold of the 22nm FDSOI SRAM cell. The effects of different LET values and different incident conditions on the single event upset of a 22nm FDSOI SRAM cell are compared. The results show that whether the 22nm FDSOI SRAM cell is single event inversion depends on the transient current peak value generated after heavy ion incidence. For the 22nm FDSOI SRAM cell, the critical current peak value is about 0.011mA. Comparing the single event inversion thresholds at different incident positions, it is found that compared to the center of the channel, when a single event is incident on the channel-drain PN junction of an off-state N-type FDSOI device, the SRAM cell is more prone to single event inversion.

A Compact Analytical Drain Current Model of Fully Depleted SOI MOSFETs with Lightly Doped N- underneath the N+ Source Region

In this work, we report a 2-D analytical model for threshold voltage and drain current of fully depleted silicon-on-insulator (SoI) metal oxide semiconductor field-effect transistor (MOSFET) with lightly doped N- underneath the N+ source region. This model considers the effect of oxide thickness, source doping variations and silicon film thickness. The accuracy of the proposed model is verified using 2-D numerical simulations in terms of surface potential, threshold voltage and drain current. In comparison with the conventional FD SOI devices, the proposed model predicts that modified source based FD SOI structure gives better OFF-state current, improved ON-state to OFF-state current (ION/IOFF ~ 109) ratio.

Modelling and analysis of gate leakage current and its wafer level variability in advanced FD-SOI MOSFETs

The gate leakage current in advanced FD-SOI devices are investigated using systematic measurements on multiple geometry devices from 14 nm node. A simple model with an equivalent trapezoidal barrier based on WKB approximation is introduced and verified on the different measurements. The wafer level variability of the leakage current is explored using statistical modelling and the simple model for gate leakage current. The pure physical sources of variation are identified and the scaling trends of the standard deviations of the sources are analysed. The methodology and models have been validated also on 28 nm node devices.

Multisubband Ensemble Monte Carlo Analysis of Tunneling Leakage Mechanisms in Ultrascaled FDSOI, DGSOI, and FinFET Devices

Leakage phenomena are increasingly affecting the performance of nanoelectronic devices, and therefore, advanced device simulators need to include them in an appropriate way. This paper presents the modeling and implementation of direct source-to-drain tunneling (S/D tunneling), gate leakage mechanisms (GLMs) accounting for both direct tunneling and trap-assisted tunneling, and nonlocal band-to-band tunneling (BTBT) phenomena in a multissubband ensemble Monte Carlo (MS-EMC) simulator along with their simultaneous application for the study of ultrascaled fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. We find that S/D tunneling is the prevalent phenomena for the three devices, and it is increasingly relevant for short-channel lengths.

Transient Response of 0.18-<inline-formula> <tex-math notation="LaTeX">${\mu}$ </tex-math> </inline-formula>m SOI MOSFETs and SRAM Bit-Cells to Heavy-Ion Irradiation for Variable SOI Film Thickness

In this paper, the effect of silicon-on-insulator (SOI) thickness scaling in fully and partially depleted SOI (FD-SOI and PD-SOI) devices is analyzed for their transient response to heavy-ion irradiation. We have analyzed radiation performance of FD-/PD-SOI MOSFETs and 6-T SRAM bit-cells, conforming to 0.18- $\mu \text{m}$ technology node, using calibrated 2-D TCAD simulations. We, for the first time, report here that while SRAMs designed with FD-SOI devices have superior hardness to heavy-ion radiation, they are also more sensitive to SOI film thickness than the SRAMs designed with PD-SOI devices. The slopes of the critical linear energy transfer (LETC) to SOI film thickness curves are +1000 and −950 000 $\text {MeV}\cdot \text {cm/mg}$ for PD-SOI and FD-SOI devices at 1.8V supply voltage ( ${V} _{\text {DD}}$ ), respectively. The negative slope for FD-SOI device indicates better radiation performance for thinner silicon films, while a positive slope in PD-SOI device indicates better radiation performance with thicker silicon films. We further investigated the effect of ambient temperature and supply voltage ( ${V} _{\text {DD}}$ ) on SOI thickness scaled FD-/PD-SOI devices. We show that increasing ${V} _{\text {DD}}$ results in increased generated charge due to the heavy-ion at transistor level, whereas LETC of the SRAM bit-cell improves with increasing ${V} _{\text {DD}}$ . We further highlight that the heavy-ion radiation response as a function of ambient temperature depends not only on the thickness of the SOI film but also on the LET of the impinging heavy-ion.

Source-to-Drain Tunneling Analysis in FDSOI, DGSOI, and FinFET Devices by Means of Multisubband Ensemble Monte Carlo

The inclusion of quantum effects in the transport direction plays an important role in the extensive research of ultrascaled electronic devices. In this context, it is necessary to study how these phenomena affect different technological architectures in order to conclude which one can be the best candidate to replace standard technology. This paper presents the implementation of direct source-to-drain tunneling effect in a multisubband ensemble Monte Carlo simulator showing its influence in different structures such as fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. The differences in the potential profile and the electron distribution in the subbands for these architectures modify the number of electrons affected by this quantum mechanism and, therefore, their short-channel behavior.

(Invited) Extending Advanced CMOS Scaling with SiGe Channel Materials

Advanced CMOS Scaling has benefited from the introduction of novel materials and integration techniques over the past two decades. Consumer demand for more connectivity and real-time information continues to drive the need for product solutions with advanced power management and increased functionality while maintaining low cost. New device architectures such as FINFET and Fully Depleted Silicon-On-Insulator are part of the solution, however these device architectures still rely on advanced channel strain engineering to meet power, performance, and scaling requirements. The use of SiGe as a channel material is attractive due to enhanced mobility and compatibility with standard CMOS processing. PFET drive current enhancement has already been realized to enable platforms based on high performance planar FDSOI devices, while SiGe as part of the channel is also a top solution to enable next generation FINFET and Gate-All-Around devices. In this invited paper we will provide an in-depth look into the device benefits and challenges of SiGe as a channel material.

(Invited) Extending Advanced CMOS Scaling with SiGe Channel Materials

Advanced CMOS Scaling has benefited from the introduction of novel materials and integration techniques over the past two decades. Consumer demand for more connectivity and real-time information continues to drive the need for product solutions with advanced power management and increased functionality while maintaining low cost. New device architectures such as FINFET and Fully Depleted Silicon-On-Insulator are part of the solution, however these device architectures still rely on advanced channel strain engineering to meet power, performance, and scaling requirements. The use of SiGe as a channel material is attractive due to enhanced mobility and compatibility with standard CMOS processing. PFET drive current enhancement has already been realized to enable platforms based on high performance planar FDSOI devices, while SiGe as part of the channel is also a top solution to enable next generation FINFET and Gate-All-Around devices. In this invited paper we will provide a look into the device benefits and challenges of SiGe as a channel material.

Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition

This work examines the effects of heavy-ion impact under temperature variation. A NMOS device in 32nm bulk and 28nm FDSOI were analysed through TCAD simulations. In order to overcome the temperature effects, both devices were conducted to the Zero Temperature Coefficient (ZTC) condition. The results demonstrate a reduction from 5% up to 18% on the total collected charge and lower variation due to temperature fluctuation when the devices are operating in ZTC condition.

(Invited) VLSI-CMOS Device Technology Scaling Landscape Based on Fully-Depleted SOI and 3D-FinFET Technologies for the Internet of Everything Era

System- and process-level innovations based on VLSI-CMOS technologies are the drivers to continue Moore’s Law. Especially in the last decade an ever-increasing component integration on SoC’s has driven cost scaling and will continue to do so while approaching the IoT and wearable device area. To keep pace with the manufacturing cost per device scaling an acceleration of new processing methods, concepts and materials has been introduced, such as local strained Si, high-k metal gate, ultra-low-k, 3D FinFET and FDSOI devices. New integration techniques like double and quadruple patterning are needed since EUV lithography cannot be easy introduced in high volume manufacturing. The inflection on the cost per gate trend can be intercepted by differentiated technologies that serve markets for the respective applications such as 22nm and 12nm FDSOI. Those technologies offer a wide variety and individualism for designs to serve the IoT/E era perfectly. SoC innovations need to focus on 3D multi-die package integrations on system level.

The Challenge of Measuring Strain in FDSOI Device Structures – HRXRD as a Potential Method of Resolution

The strain state of Si1‐xGex/SiO2 dummy structures on FDSOI wafers is non‐destructively characterized by HRXRD reciprocal space mapping. A transition from biaxial to uniaxial strain is detected on narrow condensed Si1‐xGex lines with shallow trench isolation (STI), revealing an increasing in‐plane elastic strain relaxation perpendicular to the trenches with decreasing line width, but no strain relaxation parallel to the trenches. The degree of crystallinity of Si1‐xGex lines degrades with increasing annealing temperature and time. An additional elastic strain reduction appears in the direction parallel to the STI trenches after deposition of source‐drain Si1‐yGey islands between dummy gates. The separation of the Si1‐xGex peaks from Si1‐yGey remains unresolved if x and y are close to each other.