22nm FDSOI SRAM single event upset simulation analysis

Abstract

This article uses Sentaurus TCAD to establish the 3D device model of NMOS and PMOS under the 22nm FDSOI process, and establishes the 3D model of the 22nm FDSOI SRAM cell through this model. This model is used to numerically simulate the single event upset LET threshold of the 22nm FDSOI SRAM cell. The effects of different LET values and different incident conditions on the single event upset of a 22nm FDSOI SRAM cell are compared. The results show that whether the 22nm FDSOI SRAM cell is single event inversion depends on the transient current peak value generated after heavy ion incidence. For the 22nm FDSOI SRAM cell, the critical current peak value is about 0.011mA. Comparing the single event inversion thresholds at different incident positions, it is found that compared to the center of the channel, when a single event is incident on the channel-drain PN junction of an off-state N-type FDSOI device, the SRAM cell is more prone to single event inversion.