Very Low Temperature Tensile and Selective Si:P Epitaxy for Advanced CMOS Devices

Abstract

We demonstrate the feasibility of selectively growing highly doped and tensile-strained Si:P layers at temperatures 500°C or less on each side of advanced n-type MOS devices. To that end, we used a Cyclic Deposition Etch (CDE) strategy instead of a conventional “co-flow” approach fit for the high temperature (> 600°C) Selective Epitaxial Growth (SEG) of t-SiP films. A high order silicon precursor was used together with PH3 to benefit from high t-Si:P growth rates at 500°C and less. Selective etchings were performed with Cl2 as an etchant gas, as it yielded much higher etch rates than HCl. We first investigated the blanket growth of t-SiP on fullsheet Si wafers. 5 to 15 times higher higher growth rates than with standard precursors were obtained at low temperatures with our new HOS silicon precursor. We then investigated the etching efficiency of Cl2, with several tens of nanometers per minutes etch rates achieved at very low temperatures. Using a CDE strategy, we then probed phosphorus incorporation in blanket t-Si:P films on fullsheet wafers. High quality and smooth t-SiP layers with up to 5.4%, 4.3% and 5.8% of P and sheet resistances as low as 0.33, 0.27 and 0.21 mohm.cm were obtained at 500°C, 475°C and 450°C, respectively. We then tested our CDE SiP process for SEG, first on test structures then on each side of real FD-SOI devices, with smooth, high quality, tensile SiP layers grown at 500°C with 4.5% of P.