Abstract
With hybrid bonding pitch reduction, many challenges are arising such as optimized metrology measurement, bonding wave propagation understanding and hybrid surface characterization. By analyzing incoming wafer and how tool setting impacts bonding, overlay values below 110 nm for production wafers can be achieved with 100% electrical yield. Hybrid bonding extends further to IC Logic application or Memory and not only CMOS image sensor. For some of those products, the temperature of usual post bonding thermal annealing (400°C) cannot be applied. Consequently, many studies have been performed on developing low-temperature bonding. To add flexibility to hybrid bonding, new processes such as Surface Activation Bonding (SAB) and Die to Wafer bonding (D2W) have been developed to fit heterogenous integration.
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