Fault Masking Research Articles

Squeeziness for non-deterministic systems

Failed Error Propagation greatly reduces the effectiveness of Software Testing by masking faults present in the code. This situation happens when the System Under Test executes a faulty statement, the state of the system is affected by this fault, but the expected output is observed. Therefore, it is a must to assess its impact in the testing process. Squeeziness has been shown to be a useful measure to assess the likelihood of fault masking in deterministic systems. The main goal of this paper is to define a new Squeeziness notion that can be used in a scenario where we may have non-deterministic behaviours. The new notion should be a conservative extension of the previous one. In addition, it would be necessary to evaluate whether the new notion appropriately estimates the likelihood that a component of a system introduces Failed Error Propagation. We defined our black-box scenario where non-deterministic behaviours might appear. Next, we presented a new Squeeziness notion that can be used in this scenario. Finally, we carried out different experiments to evaluate the usefulness of our proposal as an appropriate estimation of the likelihood of Failed Error Propagation. We found a high correlation between our new Squeeziness notion and the likelihood of Failed Error Propagation in non-deterministic systems. We also found that the extra computation time with respect to the deterministic version of Squeeziness was negligible. Our new Squeeziness notion is a good measure to estimate the likelihood of Failed Error Propagation being introduced by a component of a system (potentially) showing non-deterministic behaviours. Since it is a conservative extension of the original notion and the extra computation time needed to compute it, with respect to the time needed to compute the former notion, is very small, we conclude that the new notion can be safely used to assess the likelihood of fault masking in deterministic systems.

Test Point Insertion for Multi-Cycle Power-On Self-Test

Under the functional safety standard ISO26262, automotive systems require testing in the field, such as the power-on self-test (POST) . Unlike the production test, the POST requires reducing the test application time to meet the indispensable test quality (e.g., >90% of latent fault metric) of ISO26262. This article proposes a test point insertion technique for multi-cycle power-on self-test to reduce the test application time under the indispensable test quality. The main difference to the existing test point insertion techniques is to solve the fault masking problem and the fault detection degradation problem under the multi-cycle test. We also present the method to identify a user-specified amount of test points that could achieve the most scan-in pattern reduction for attaining a target test coverage. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average to achieve 90% stuck-at fault coverage confirming the effectiveness of the proposed method.

Sixer: A low-overhead, fully-distributed test scheme with guaranteed delivery of packets in networks-on-chip

The guaranteed delivery of application packets from source to destination in a network-on-chip (NoC) is increasingly becoming an essential design issue. Channel faults may cause a significant amount of packet loss and subsequently degrade the system’s performance. In particular, open-channel defects threaten the loss of reliability, yield, and service quality. Hence, their detection and localization during the system’s runtime are highly needed. However, coexistent short-channel faults might mitigate the threats to a certain extent. This paper presents a low-cost test method that detects open-channel faults to preserve the connectivity between a source and destination pair in NoCs. The procedure is extended to address the channel’s self-repairing mode by covering the short-channel defects via fault masking. Further, a fully distributed test-scheduling technique named “Sixer” is presented to reduce the test cost and make the scheme scalable with NoCs. Experimental results show hardware synthesis incurs nearly 6.72% and 21.85% area overhead while single and multiple channel-fault models are assumed, respectively. The test method takes 8 and 38 clocks for the same fault models. Also, fault simulation shows full and (nearly 95%) fault coverage for these models. Online evaluation of the “Sixer” reveals various performance metrics. A detailed comparison study shows the proposed scheme improves hardware area and test-time overhead up to 66.12% and 97%, respectively. Simultaneously, performance overhead is improved by 43.78%, 54.75%, and 62.97% concerning packet loss, latency, and energy consumption, respectively.

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics

The effects of soft error in combinational logics are challenged by decreasing the feature size of transistors in nanoscale technologies. Moreover, the single event transients (SETs) caused by particle strikes, manifesting multiple event transients (METs), are expectable, as well. Coping with this problem is the end of CLEAR using a cross-layer method as an effective way to mitigate the rate of double event transients (DETs) in combinational logic. First, an algorithm is proposed based on local displacements and linear programming (LP) optimization problem, which locates the cells in the best way from the DETs point of view. Next, two hardening methods are proposed based on resizing and fault masking. Finally, one of these two methods is applied to the aforesaid algorithm results, modified layout, considering the given design parameters. Experimental studies reveal a reduction of 42.9% on average in DETs rate, which can be improved up to 51.1% and 68.9% by applying two aforementioned hardening methods with some negligible overhead.

Hybrid and Double Modular Redundancy (DMR)-Based Fault-Tolerant Carry Look-Ahead Adder Design

The adder is an essential component of data paths, and as a result of the shrinking size of electronic devices, it is becoming more susceptible to manufacturing defects and soft errors. Thus, the design of fault-tolerant adders is crucial to the correct operation of arithmetic circuits. In this paper, we propose different fault-tolerant carry look-ahead adder designs against single-bit soft errors based on double modular redundancy DMR and hybrid fault-tolerant schemes. In DMR-based design, we combine a partial hardware redundancy scheme with a protected C-element to achieve full soft error masking, while in the hybrid design, we employ a partial hardware redundancy combined with a parity prediction scheme to improve fault tolerance capability of the adder while reducing area overhead. We use two different voter circuits for merging the partial hardware redundancy into the carry generation logic and to achieve higher fault masking rate and lower area overhead in comparison with existing approaches. Simulation results show that the proposed design schemes take precedence over other schemes in terms of failure rate, area overhead and delay overhead.

A High-Reliability Redundancy Scheme for Design of Radiation-Tolerant Half-Duty Limited DC-DC Converters

Redundancy techniques are commonly used to design radiation- and fault-tolerant circuits for space applications, to ensure high reliability. However, higher reliability often comes at a cost of increased usage of hardware resources. Triple Modular Redundancy (TMR) ensures full single fault masking, with a >200% power and area overhead cost. TMR/Simplex ensures full single fault masking with a slightly more complicated circuitry, inefficient use of resource and a >200% power and area overhead cost, but with higher reliability than that of TMR. In this work, a high-reliability Spatial and Time Redundancy (TR) hybrid technique, which does not abandon a working module and is applicable for radiation hardening of half-duty limited DC-DC converters, is proposed and applied to the design of a radiation-tolerant digital controller for a Dual-Switch Forward Converter. The technique has the potential of double fault masking with a <2% increase in resource overhead cost compared to TMR. Moreover, for a Simplex module failure rate, λ, of 5%, the Reliability Improvement Factor (RIF) over the Simplex system is 20.8 and 500 for the proposed technique’s two- and three-module implementations, respectively, compared to a RIF over the Simplex system of only 7.25 for TMR and 14.3 for the regular TMR/Simplex scheme.

Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation

This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.

Diagnosis of Open-Phase Faults for a Five-Phase PMSM Fed by a Closed-Loop Vector-Controlled Drive Based on Magnetic Field Pendulous Oscillation Technique

An online diagnostic approach of open-phase faults for a five-phase permanent magnet synchronous motor (PMSM) fed by a closed-loop vector-controlled drive is presented in this article. This approach is accomplished based on the magnetic field pendulous oscillation (MFPO) phenomenon, in which a significant “swing-like” pendulous oscillation in the magnetic field is observed in case of open-phase faults. According to an analysis of the signatures of MFPO patterns under faulty conditions, all possible open-phase faults are detected, including single-phase open faults, two-adjacent phase open faults, and two-nonadjacent phase open faults. Moreover, this approach is capable of localizing the faulted phase/phases by further extracting the phase angle features of MFPO angular position waveforms under faulty conditions. Meanwhile, in order to minimize the number of sensors to reduce the implementation cost of this diagnostic approach, a phase-locked loop technique is developed to overcome the fault masking difficulties associated with the compensation action of the closed-loop vector-controlled drive. As a result, this diagnostic approach only requires four current sensors and a speed sensor, which are typically already available in five-phase PMSM drive systems for control purposes. Finally, experimental results demonstrate the effectiveness of the presented approach.

Implementation of System Operation Modes for Health Management and Failure Prognosis in Cyber-Physical Systems.

Cyber-physical systems (CPSs) have sophisticated control mechanisms that help achieve optimal system operations and services. These mechanisms, imply considering multiple signal inputs in parallel, to timely respond to varying working conditions. Despite the advantages that control mechanisms convey, they bring new challenges in terms of failure prevention. The compensatory action the control exerts cause a fault masking effect, hampering fault diagnosis. Likewise, the multiple information inputs CPSs have to process can affect the timely system response to faults. This article proposes a failure prognosis method, which combines time series-based forecasting methods with statistically based classification techniques in order to investigate system degradation and failure forming on system levels. This method utilizes a new approach based on the concept of the system operation mode (SOM) that offers a novel perspective for health management that allows monitoring the system behavior, through the frequency and duration of SOMs. Validation of this method was conducted by systematically injecting faults in a cyber-physical greenhouse testbed. The obtained results demonstrate that the degradation and fault forming process can be monitored by analyzing the changes of the frequency and duration of SOMs. These indicators made possible to estimate the time to failure caused by various failures in the conducted experiments.

Approximate Triple Modular Redundancy: A Survey

In recent years, approximate computing (AC) has attracted attention owing to its tradeoff between the exactness of computations and performance gains. AC has also been probed for the technique of Triple modular redundancy (TMR). TMR is a well-known fault masking methodology, with associated overheads, widely used in systems of different nature and at different levels. E.g.: layout-level, gate-level, HW-module level, software. At hardware level, through exploitation of AC the 200% area overhead problem due to triplication of the original modules in TMR can be reduced. By approximating the modules of TMR while ensuring that at least two of the approximate modules do not differ from the original module for every input vector, the facilitation of fault masking can lead to overhead reduction. Hence, approximate TMR (ATMR) aims to achieve cost-effective reliability. Nevertheless, due to the extensive search space, computational complexity, and principal fault masking function of ATMR, designing an ATMR is a challenging task. An ATMR technique must be scalable so that it can be easily adopted by circuits having large number of inputs and the extraction of ATMR modules remains computationally inexpensive. Compared with TMR, due to the inclusion of approximations, ATMR is more vulnerable to errors, and hence, the design technique must ensure awareness of input-criticality. To the best of the authors' knowledge, none of the existing survey articles on AC has reported on ATMR. Therefore, in this work, ATMR design techniques are thoroughly surveyed and qualitatively compared. Moreover, design considerations and challenges for designing ATMR are discussed.

Design of fault tolerant majority voter for error resilient TMR targeting micro to nano scale logic

The shrinking size of transistors for satisfying the increasing demand for higher density and low power has made the VLSI circuits more vulnerable to faults. Therefore, new circuits in advanced VLSI technology have forced designers to use fault tolerant techniques in safety-critical applications. Also, the presence of some faults (not permanent) due to the complexity of the nanocircuit or its interaction with software results in malfunctioning of circuits. The fault tolerant scheme, where majority voter plays the core role in triple modular redundancy (TMR), is being implemented increasingly in digital systems. This work targets to implement a different fault tolerant scheme of majority voter for the implementation of TMR using quantum-dot cellular automata (QCA), viable alternative nanotechnology to CMOS VLSI. The fault masking ability of various voter designs has been analysed in details. The fault masking ratio of the proposed voter (FMV) is 66% considering single/multiple faults. Simulation results establish the validation of proposed logic in QCA which targets nano-scale devices. The proposed logic is also suitable for conventional CMOS technology, which is verified with the Cadence tool.

Design of fault tolerant majority voter for error resilient TMR targeting micro to nano scale logic

The shrinking size of transistors for satisfying the increasing demand for higher density and low power has made the VLSI circuits more vulnerable to faults. Therefore, new circuits in advanced VLSI technology have forced designers to use fault tolerant techniques in safety-critical applications. Also, the presence of some faults (not permanent) due to the complexity of the nanocircuit or its interaction with software results in malfunctioning of circuits. The fault tolerant scheme, where majority voter plays the core role in triple modular redundancy (TMR), is being implemented increasingly in digital systems. This work targets to implement a different fault tolerant scheme of majority voter for the implementation of TMR using quantum-dot cellular automata (QCA), viable alternative nanotechnology to CMOS VLSI. The fault masking ability of various voter designs has been analysed in details. The fault masking ratio of the proposed voter (FMV) is 66% considering single/multiple faults. Simulation results establish the validation of proposed logic in QCA which targets nano-scale devices. The proposed logic is also suitable for conventional CMOS technology, which is verified with the Cadence tool.

Nonlinear Adaptive Hybrid Compensation for Actuator-Sensor Compound Faults of Non-Gaussian Uncertain Systems

This paper presents a hybrid fault-tolerant control (FTC) method to handle actuator-sensor compound faults in non-Gaussian uncertain stochastic systems with approximation errors. Considering that multi-source nonlinearities of a class of stochastic systems cannot be approximated by a unified method, fuzzy logic is used to linearize nonlinear parameters, and the Lipschitz condition helps to proof the stability of FTC systems with nonlinear sensing functions. Moreover, to handle compound faults, an adaptive hybrid fault compensation scheme is devised. When only a sensor fault occurs, the feedback contains the fault information, and a feedback error composite function in the controller direct compensates the fault passively. When multiple actuator faults and a sensor fault occur, an adaptive fusion observer simultaneously implements sensor fault masking and actuator fault estimation, and then an active-passive hybrid FTC algorithm uses a compensation function and fault estimation to perform both passive compensation of the sensor fault and active FTC of actuator faults. Furthermore, an adaptive algorithm that resembles the animal predation behavior makes the controller more sensitive to incipient fault deviations. Lyapunov functions prove the robust stability of the proposed fault tolerant systems with approximation errors, and simulation experiment verifies the performance compared to a state-of-the-art method.

Optimal Release Time Determination in Intuitionistic Fuzzy Environment Involving Randomized Cost Budget for SDE-Based Software Reliability Growth Model

To enhance the accuracy of estimating the reliability of the software, it becomes essential to count upon the proportion of faults that are predominantly dormant due to fault masking. In addition to that, the software managers and developers primarily aim at obtaining the date of product release by attaining a compromise between maximizing the reliability level and minimizing the product development cost. Keeping in mind the above requirements for reliability estimation, a stochastic differential equation-based software reliability growth model (SRGM) is developed for open-source software. Multi-release of the SRGM is formulated in detail taking into consideration the effect of bug classification. An innovative safe technique called Rx is deployed which is capable of recovering programs from both deterministic and indeterministic bugs. The optimal date of product release is obtained via a parabolic multi-objective chance-constrained nonlinear optimization problem in the parabolic intuitionistic fuzzy set environment. The optimization model framed to determine the time of product release is critically analyzed from both optimistic and pessimistic viewpoints of the developer. The results manifest the better performance of the model proposed in comparison with some preexisting SRGMs reported in the literature. Moreover, the exemplified methodology corresponding to the attainment of the optimal date for product release is well established as it is truly capable of taking into consideration, the level of tolerance of the developer pertaining to variations in both reliability and cost.

Approximate TMR based on successive approximation and loop perforation in microprocessors

This work presents an approximate triple modular redundancy (ATMR) method based on successive approximation and loop perforation. Successive approximation consists of loop-based algorithms that improve their output quality on every iteration execution. By manipulating the number of executed iterations, a designer can balance output quality and execution time performance. The proposed technique exploits this approximate computing paradigm combined with data size and precision reduction to minimize traditional triple modular redundancy (TMR) costs while maintaining a good fault masking capability. A number of ATMR configurations are presented and tested under laser fault injection to evaluate their fault masking capability. The benchmarks are implemented as embedded software in the ARM Cortex A9 processor of a Xilinx Zynq-7000 series board. The proposed technique was able to improve the execution time overhead with the usage of approximations, with an acceptable fault masking rate.

Single event transient sensitivity analysis of different 32 nm CMOS majority voters designs

As a consequence of the technology scaling, the reduced amount of energy needed to store information impacts the Linear Energy Transfer Threshold (LETth), implying in circuits more sensitive to radiation faults. Hardware redundancy techniques such as the Triple Modular Redundancy are constantly used to mitigate this problem. However, the weakness of the redundancy technique is the voter circuit, and for this reason, alternative designs have been proposed in the literature to improve the robustness of this block. This work investigates the robustness of different majority voter topologies in the presence of Single Event Transient (SET). A layout-level analysis using stick diagrams is fulfilled to analyze the impact a SET causes in diffusion areas shared by transistors, and a fault masking ratio is used to measure the voter robustness. Then an electrical-level analysis was done based on the information provided from the previous study to investigate the threshold LET. The results obtained in this study shown that the topologies can endure a LET up to 1.86 MeV·cm−2/mg considering the 32 nm CMOS technology.

Practical fault resilient hardware implementations of AES

Security is a challenging issue in resource-constrained applications, e.g. in an embedded system. This study focused on practical lightweight fault-tolerant strategies for hardware implementation of Advanced Encryption Standard (AES) to mitigate the-reliability issue of secure architectures. In this work, a-fault-tolerant architecture called configurable fault-tolerant AES (CFTA), and its variants, called robust CFTA (R-CFTA), R-CFTA+, high throughput CFTA (HT-CFTA), HT-CFTA4R, HT-CFTA8R, and HT-CFTA+, are introduced. Proposed approaches exploit the-inherent parallel architecture of AES for employing redundancy at low cost. CFTA and HT-CFTA can tolerate all single permanent and transient faults in the-AES blocks and also all multiple permanent and transient faults in the-same block. R-CFTA upgrades the-fault-tolerant aspect of CFTA and HT-CFTA and it is also able to tolerate all single- and multiple-transient faults in two AES functional blocks during a round. The proof is provided to show the fault masking ability of provided architectures. Furthermore, R-CFTA+ and HT-CFTA+, which are suitable for high-security sensitive applications are suggested. In addition, the proposed fault-tolerant designs are implemented on both field programmable gate array and application-specific integrated circuit platforms, and their implementation area, frequency, and throughput are discussed and compared with other related works. Moreover, system-efficiency, as an important design metric, is reported for proposed structures.

Special section: Extended papers from REFSQ 2018

Context:Testing is the main validation technique used to increase the reliability of software systems. The effectiveness of testing can be strongly reduced by Failed Error Propagation. This situation happens when the System Under Test executes a faulty statement, the state of the system is affected by this fault, but the expected output is observed. Squeeziness is an information theoretic measure designed to quantify the likelihood of Failed Error Propagation and previous work has shown that Squeeziness correlates strongly with Failed Error Propagation in white-box scenarios. Despite its usefulness, this measure, in its current formulation, cannot be used in a black-box scenario where we do not have access to the source code of the components.Objective:The main goal of this paper is to adapt Squeeziness to a black-box scenario and evaluate whether it can be used to estimate the likelihood that a component of a software system introduces Failed Error Propagation.Method: First, we defined our black-box scenario. Specifically, we considered the Failed Error Propagation that a component introduces when it receives its input from another component. We were interested in this since such fault masking makes it more difficult to find faults in the previous component when testing. Second, we defined our notion of Squeeziness in this framework. Finally, we carried out experiments in order to evaluate our measure.Results: Our experiments showed a strong correlation between the likelihood of Failed Error Propagation and Squeeziness.Conclusion: We can conclude that our new notion of Squeeziness can be used as a measure that estimates the probability of Failed Error Propagation being introduced by a component. As a result, it has the potential to be used as a measure of testability, allowing testers to assess how easy it is to test either the whole system or a single component. We considered a simple model (Finite State Machines) but the notions and results can be extended/adapted to deal with more complex state-based models, in particular, those containing data.

Building ATMR circuits using approximate library and heuristic approaches

Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial hardware replication where designers can explore reduced area overhead combined with some compromise on fault masking. This work presents a novel approach for implementing approximate TMR that combines the approximate gate library (ApxLib) technique with heuristics. The algorithm initially defines the gates to be approximated using testability and observability measures and then chooses the gate transformation based on the bits difference. Experimental results showed good trade-off between the ATMR schemes efficiency in terms of area and fault masking and the computational effort needed to generate them.