Practical fault resilient hardware implementations of AES

Abstract

Security is a challenging issue in resource-constrained applications, e.g. in an embedded system. This study focused on practical lightweight fault-tolerant strategies for hardware implementation of Advanced Encryption Standard (AES) to mitigate the-reliability issue of secure architectures. In this work, a-fault-tolerant architecture called configurable fault-tolerant AES (CFTA), and its variants, called robust CFTA (R-CFTA), R-CFTA+, high throughput CFTA (HT-CFTA), HT-CFTA4R, HT-CFTA8R, and HT-CFTA+, are introduced. Proposed approaches exploit the-inherent parallel architecture of AES for employing redundancy at low cost. CFTA and HT-CFTA can tolerate all single permanent and transient faults in the-AES blocks and also all multiple permanent and transient faults in the-same block. R-CFTA upgrades the-fault-tolerant aspect of CFTA and HT-CFTA and it is also able to tolerate all single- and multiple-transient faults in two AES functional blocks during a round. The proof is provided to show the fault masking ability of provided architectures. Furthermore, R-CFTA+ and HT-CFTA+, which are suitable for high-security sensitive applications are suggested. In addition, the proposed fault-tolerant designs are implemented on both field programmable gate array and application-specific integrated circuit platforms, and their implementation area, frequency, and throughput are discussed and compared with other related works. Moreover, system-efficiency, as an important design metric, is reported for proposed structures.