Fault Injection Simulation Research Articles

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets

Transient errors induced by radiations cause bit-flips in flip-flops (flip-flop soft errors). Modeling the error resilience level of a target system for flip-flop soft errors is a crucial step to achieve a cost-effective error resilience solution. This step often requires a significant amount of time and effort for a large number of fault injection simulations. As technology scales, the required effort grows in a new dimension with the increased probability of multi-bit upsets (MBUs). In this work, we present a new estimation model that predicts the resulting error resilience levels for the flip-flop MBU cases. This estimation model only requires the measured soft error effects of the single-bit upset (SBU) cases. This model uses two strategies to address how multiple bit-flips that happen simultaneously in a system affects the outcome of application execution. We evaluate the accuracy level of the MBU estimation model using actual fault injection results on two different processor cores. The two main strategies in our estimation model improve the accuracy levels by more than 7×.

Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree

The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.

Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient Block Cipher KLEIN Benchmarked on FPGA

Security-sensitive usage models, such as implantable and wearable medical devices are prone to algorithmic cryptographic attacks as well as malicious implementation attacks. The cryptographic algorithms in these cryptosystems, such as lightweight block ciphers utilized in constrained applications, face significant tradeoff between the high level of security and the efficiency of their implementation metrics. For thwarting fault analysis attacks, among effective variants of active implementation attacks, and also to detect natural faults, efficient fault diagnosis schemes for these lightweight block ciphers are essential. In this paper, for the first time, we propose error detection schemes for lightweight block cipher, KLEIN, to ameliorate its error resiliency with low hardware complexity. The proposed fault diagnosis architectures are for linear and nonlinear components of this cipher. We also consider the notion of fault space transformation for lightweight cryptography and present its potential complications. The implementation of the proposed schemes through variants of Xilinx field-programmable gate arrays and the error coverage assessed with fault injection simulations show the effectiveness of the proposed schemes with acceptable footprints.

ADAS 시스템의 고장 주입 시뮬레이션 환경 개발 및 고장 안전성 평가 사례 연구

ADAS 시스템의 고장 주입 시뮬레이션 환경 개발 및 고장 안전성 평가 사례 연구

Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA

Achieving secure high-performance implementations for constrained applications such as implantable and wearable medical devices are a priority in efficient block ciphers. However, security of these algorithms is not guaranteed in the presence of malicious and natural faults. Recently, a new lightweight block cipher, Midori, has been proposed that optimizes the energy consumption besides having low latency and hardware complexity. In this paper, fault diagnosis schemes for variants of Midori are proposed. To the best of the authors’ knowledge, there has been no fault diagnosis scheme presented in the literature for Midori to date. The fault diagnosis schemes are provided for the nonlinear S-box layer and for the round structures with both 64-bit and 128-bit Midori symmetric key ciphers. The proposed schemes are benchmarked on a field-programmable gate array and their error coverage is assessed with fault-injection simulations. These proposed error detection architectures make the implementations of this new low-energy lightweight block cipher more reliable.

Evaluation of transient errors in GPGPUs for safety critical applications: An effective simulation-based fault injection environment

General Purpose Graphics Processing Units (GPGPUs) are increasingly adopted thanks to their high computational capabilities. GPGPUs are preferable to CPUs for a large range of computationally intensive applications, not necessarily related to computer graphics. Within the high performance computing context, GPGPUs must require a large amount of resources and have plenty execution units. GPGPUs are becoming attractive for safety-critical applications where the phenomenon of transient errors is a major concern. In this paper we propose a novel transient error fault injection simulation methodology for the accurate simulation of GPGPUs applications during the occurrence of transient errors. The developed environment allows to inject transient errors within all the memory area of GPGPUs and into not user-accessible resources such as in streaming processors combinational logic and sequential elements. The capability of the fault injection simulation platform has been evaluated testing three benchmark applications including mitigation approaches such as Duplication With Comparison, Triple Modular Redundancy and Algorithm Based Fault Tolerance. The amount of computational costs and time measured is minimal thus enabling the usage of the developed approach for effective transient errors evaluation.

An RTOS-based Fault Injection Simulator for Embedded Processors

Evaluating embedded systems vulnerability to faults injection attacks has gained importance in recent years due to the rising threats they bring to chips security. The task is particularly important for micro-controllers since they have lower resistance to fault attacks compared to hardware-based cryptosystems. This paper reviews recent embedded fault injection simulators from literature and presents an embedded high-level fault injection mechanism based on a Real-Time Operating System (RTOS). The approach aims to be architecture-independent and portable to 32-bit micro-controllers and embedded processors. The proposed mechanism, primarily targets realistic fault attack scenarios on memory locations, is adapted to timed and event-based fault injection. A Differential Fault Attack (DFA) was mounted on a popular ARM-based micro-controller running FreeRTOS to illustrate the proposed mechanism. The aim is also to bridge the embedded fault injection simulation mechanism efficiently to a computer-based cryptanalysis and to highlight the importance of physically protecting the memory and integrating data-specific countermeasures.

Fault Attacks Resistant Architecture for KECCAK Hash Function

The KECCAK cryptographic algorithms widely used in embedded circuits to ensure a high level of security to any systems which require hashing as the integrity checking and random number generation. One of the most efficient cryptanalysis techniques against KECCAK implementation is the fault injection attacks. Until now, only a few fault detection schemes for KECCAK have been presented. In this paper, in order to provide a high level of security against fault attacks, an efficient error detection scheme based on scrambling technique has been proposed. To evaluate the robust of the proposed detection scheme against faults attacks, we perform fault injection simulations and we show that the fault coverage is about 99,996%. We have described the proposed detection scheme and through the Field-Programmable Gate Array analysis, results show that the proposed scheme can be easily implemented with low complexity and can efficiently protect KECCAK against fault attacks. Moreover, the Field-Programmable Gate Array implementation results show that the proposed KECCAK fault detection scheme realises a compromise between implementation cost and KECCAK robustness against fault attacks.

Look up Table Based Low Power Analog Circuit Testing

In this paper, a method of low power analog testing is proposed. In spite of having Oscillation Based Built in Self-Test methodology (OBIST), a look up table based (LUT) low power testing approach has been proposed to find out the faulty circuit and also to sort out the particular fault location in the circuit. In this paper an operational amplifier, which is the basic building block in the analog circuit, is designed and is taken for testing purpose. Fault coverage is identified after fault modeling, fault injection and fault simulation. More than 93% fault coverage is achieved and there is a scope of increasing more fault coverage. Since analog testing prefaces the challenge of power dissipation during testing, some power minimization techniques like sleepy stack method and current correlation method have adhered during the testing process. Test power reduction up to 84 % is achieved in this work.

Accurate Model for Application Failure Due to Transient Faults in Caches

To select an appropriate level of error protection in caches, the impact of various protection schemes on the cache Failure In Time (FIT) rate must be evaluated for a target benchmark suite. However, while many simulation tools exist to evaluate area, power and performance for a set of benchmark programs, there is a dearth of such tools for reliability. This paper introduces a new cache reliability model called PARMA+ that has unique features which distinguish it from previous models. PARMA+ estimates a cache's FIT rate in the presence of spatial multi-bit faults, single-bit faults, temporal multi-bit faults and different error protection schemes including parity, ECC, early write-back and bit-interleaving. We first develop the model formally, then we demonstrate its accuracy. We have run reliability simulations for many distributions of large and small fault patterns and have compared them with accelerated fault injection simulations. PARMA+ has high accuracy and low computational complexity.

Soft error rate estimation of combinational circuits based on vulnerability analysis

Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making the soft error rate (SER) estimation an important challenge. In this study, a novel approach is proposed for SER estimation of combinational circuits based on vulnerability analysis. The authors introduce a concept called probabilistic vulnerability window (PVW) which is an inference of necessary conditions for a single event transient (SET) to cause observable errors in the circuit. A proposed computational framework calculates PVWs for all circuit gates in a backward-traversing algorithm enabling the circuit designers for an accurate and efficient SER estimation. Experimental results show that the proposed approach is 2× faster than the traditional SER estimation methods and keep its efficiency when it is applied for estimating the SER considering various different SET widths while runtime of traditional estimation methods increases in such cases. In addition, results verify the accuracy (average difference of 0.02) and speedup (about four orders of magnitude) of the proposed method when compared with the Monte Carlo-based fault injection simulation on ISCAS'85 benchmark circuits.

Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems

The development of extremely-constrained embedded systems having sensitive nodes such as RFID tags and nanosensors necessitates the use of lightweight block ciphers. Nevertheless, providing the required security properties does not guarantee their reliability and hardware assurance when the architectures are prone to natural and malicious faults. In this letter, error detection schemes for lightweight block ciphers are proposed with the case study of XTEA (eXtended TEA). Lightweight block ciphers such as XTEA, PRESENT, SIMON, and the like might be better suited for low-resource deeply-embedded systems compared to the Advanced Encryption Standard. Three different error detection approaches are presented and according to our fault-injection simulations, high error coverage is achieved. Finally, field-programmable gate array (FPGA) implementations of these proposed error detection structures are presented to assess their efficiency and overhead. The schemes presented can also be applied to lightweight hash functions with similar structures, making the presented schemes suitable for providing reliability to their lightweight security-constrained hardware implementations.

Formal validation of fault management design solutions

The work presented in this paper describes an approach used to develop SysML modeling patterns to express the behavior of fault protection, test the model's logic by performing fault injection simulations, and verify the fault protection system's logical design via model checking. A representative example, using a subset of the fault protection design for the Soil Moisture Active-Passive (SMAP) system, was modeled with SysML State Machines and JavaScript as Action Language. The SysML model captures interactions between relevant system components and system behavior abstractions (mode managers, error monitors, fault protection engine, and devices/switches). Development of a method to implement verifiable and lightweight executable fault protection models enables future missions to have access to larger fault test domains and verifiable design patterns. A tool-chain to transform the SysML model to jpf-statechart compliant Java code and then verify the generated code via model checking was established. Conclusions and lessons learned from this work are also described, as well as potential avenues for further research and development.

Abstractions for Executable and Checkable Fault Management Models

The work presented in this paper describes an approach used to develop SysML modeling patterns to express the logical behavior of fault protection (FP), test the model's logic via fault injection simulations, and verify the system's logical design via model checking. A FP model was architected with collaborating Statecharts that captures interactions between relevant system components (error monitors, FP engine, devices) and system behavior abstractions. Development of a method to implement verifiable and lightweight executable FP models enables future missions to have access to larger fault test domains and verifiable design patterns.

The Design of Reliable Circuits Using Logic Redundancy

With the increasing demand for more durable products, the necessity of designing more resilient products is evident. When it comes to electronic systems, many strategies have been applied to enhance the durability and performance of the operating circuits. For a long time, the main focus was to develop increasingly reliable components, however, yield enhancement techniques may not be sufficient for future technologies. As a solution to this, redundancy strategies are being introduced in order to regain reliability of circuits even if the individual components are not as reliable as desired. The use of logic redundancy and series or parallel association of transistors is proposed as a strategy in the design of fault tolerant logic gates (that are the basic elements of many complex computing structures), such as NAND and NOR. Fault injection simulations show that the reliability of these gates in the presence of random stuck-at faults may be increased by our design approach and that the strategy is extensible to more elaborate circuits.

Efficient Fault Diagnosis Schemes for Reliable Lightweight Cryptographic ISO/IEC Standard CLEFIA Benchmarked on ASIC and FPGA

Lightweight block ciphers are essential for providing low-cost confidentiality to sensitive constrained applications. Nonetheless, this confidentiality does not guarantee their reliability in the presence of natural and malicious faults. In this paper, fault diagnosis schemes for the lightweight internationally standardized block cipher CLEFIA are proposed. This symmetric-key cipher is compatible with yet lighter in hardware than the Advanced Encryption Standard and enables the implementation of cryptographic functionality with low complexity and power consumption. To the best of the authors' knowledge, there has been no fault diagnosis scheme presented in the literature for the CLEFIA to date. In addition to providing fault diagnosis approaches for the linear blocks in the encryption and the decryption of the CLEFIA, error detection approaches are presented for the nonlinear S-boxes, applicable to their composite-field implementations as well as their lookup table realizations. Through fault-injection simulations, the proposed schemes are benchmarked, and it is shown that they achieve error coverage of close to 100%. Finally, both application-specific integrated circuit and field-programmable gate array implementations of the proposed error detection structures are presented to assess their efficiency and overhead. The proposed fault diagnosis architectures make the implementations of the International Organization for Standardization/International Electrotechnical Commission-standardized CLEFIA more reliable.

An Efficient and Experimentally Tuned Software-Based Hardening Strategy for Matrix Multiplication on GPUs

Neutron radiation experiment results on matrix multiplication on graphic processing units (GPUs) show that multiple errors are detected at the output in more than 50% of the cases. In the presence of multiple errors, the available hardening strategies may become ineffective or inefficient. Analyzing radiation-induced error distributions, we developed an optimized and experimentally tuned software-based hardening strategy for GPUs. With fault-injection simulations, we compare the performance and correcting capabilities of the proposed technique with the available ones.

Analyzing the Impact of Intermittent Faults on Microprocessors Applying Fault Injection

Intermittent faults, being serious concerns for deep-submicron integrated circuits, are not well studied in the literature. This paper performs fault injection simulation to analyze the impact of intermittent faults, which is an important step towards the development of mitigation techniques for such threats.

Relyzer

Future microprocessors need low-cost solutions for reliable operation in the presence of failure-prone devices. A promising approach is to detect hardware faults by deploying low-cost monitors of software-level symptoms of such faults. Recently, researchers have shown these mechanisms work well, but there remains a non-negligible risk that several faults may escape the symptom detectors and result in silent data corruptions (SDCs). Most prior evaluations of symptom-based detectors perform fault injection campaigns on application benchmarks, where each run simulates the impact of a fault injected at a hardware site at a certain point in the application's execution (application fault site). Since the total number of application fault sites is very large (trillions for standard benchmark suites), it is not feasible to study all possible faults. Previous work therefore typically studies a randomly selected sample of faults. Such studies do not provide any feedback on the portions of the application where faults were not injected. Some of those instructions may be vulnerable to SDCs, and identifying them could allow protecting them through other means if needed. This paper presents Relyzer, an approach that systematically analyzes all application fault sites and carefully picks a small subset to perform selective fault injections for transient faults. Relyzer employs novel fault pruning techniques that prune faults that need detailed study by either predicting their outcomes or showing them equivalent to other faults. We find that Relyzer prunes about 99.78% of the total faults across twelve applications studied here, reducing the faults that require detailed simulation by 3 to 5 orders of magnitude for most of the applications. Fault injection simulations on the remaining faults can identify SDC causing faults in the entire application. Some of Relyzer's techniques rely on heuristics to determine fault equivalence. Our validation efforts show that Relyzer determines fault outcomes with 96% accuracy, averaged across all the applications studied here.

Relyzer

Future microprocessors need low-cost solutions for reliable operation in the presence of failure-prone devices. A promising approach is to detect hardware faults by deploying low-cost monitors of software-level symptoms of such faults. Recently, researchers have shown these mechanisms work well, but there remains a non-negligible risk that several faults may escape the symptom detectors and result in silent data corruptions (SDCs). Most prior evaluations of symptom-based detectors perform fault injection campaigns on application benchmarks, where each run simulates the impact of a fault injected at a hardware site at a certain point in the application's execution (application fault site). Since the total number of application fault sites is very large (trillions for standard benchmark suites), it is not feasible to study all possible faults. Previous work therefore typically studies a randomly selected sample of faults. Such studies do not provide any feedback on the portions of the application where faults were not injected. Some of those instructions may be vulnerable to SDCs, and identifying them could allow protecting them through other means if needed. This paper presents Relyzer, an approach that systematically analyzes all application fault sites and carefully picks a small subset to perform selective fault injections for transient faults. Relyzer employs novel fault pruning techniques that prune faults that need detailed study by either predicting their outcomes or showing them equivalent to other faults. We find that Relyzer prunes about 99.78% of the total faults across twelve applications studied here, reducing the faults that require detailed simulation by 3 to 5 orders of magnitude for most of the applications. Fault injection simulations on the remaining faults can identify SDC causing faults in the entire application. Some of Relyzer's techniques rely on heuristics to determine fault equivalence. Our validation efforts show that Relyzer determines fault outcomes with 96% accuracy, averaged across all the applications studied here.