Abstract

The KECCAK cryptographic algorithms widely used in embedded circuits to ensure a high level of security to any systems which require hashing as the integrity checking and random number generation. One of the most efficient cryptanalysis techniques against KECCAK implementation is the fault injection attacks. Until now, only a few fault detection schemes for KECCAK have been presented. In this paper, in order to provide a high level of security against fault attacks, an efficient error detection scheme based on scrambling technique has been proposed. To evaluate the robust of the proposed detection scheme against faults attacks, we perform fault injection simulations and we show that the fault coverage is about 99,996%. We have described the proposed detection scheme and through the Field-Programmable Gate Array analysis, results show that the proposed scheme can be easily implemented with low complexity and can efficiently protect KECCAK against fault attacks. Moreover, the Field-Programmable Gate Array implementation results show that the proposed KECCAK fault detection scheme realises a compromise between implementation cost and KECCAK robustness against fault attacks.

Highlights

  • In August 2015, the cryptographic hash algorithm SHA-3 was finalised by the National Institute of Standard and Technology (NIST), when the KECCAK algorithm was adopted

  • Various hardware implementation architectures and optimisations of KECCAK algorithm have been proposed for different applications and their performances have been evaluated by using ASIC and FPGA [3,4,5,6,7]

  • We present the hardware FPGA implementation of the proposed KECCAK architecture

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Summary

INTRODUCTION

Many error detection schemes have been implemented to make a robust hardware design and to secure cryptographic systems against faults injection attacks [12,13,14,15,16,17,18,19,20,21]. In [12] Bayat-Sarmadi et al proposed a new fault detection scheme for the KECCAK hash function This is based on rotated by a random number before each round operation, and shifted back after KECCAK operations without changing the results. We proposed a new fault detection scheme for obtaining an efficient KECCAK implementation with a high level of security against faults attacks.

Algorithm KECCAK
Implementation details of KECCAK
FPGA Implementation of KECCAK Architecture
PROPOSED FAULT DETECTION SCHEME FOR THE KECCAK
FAULT DETECTION ANALYSIS
FPGA IMPLEMENTATION
Design Original KECCAK
Findings
CONCLUSION
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