Abstract
Attacks on cryptocircuits are becoming increasingly sophisticated, requiring designers to include more and more countermeasures in the design to protect it against malicious attacks. Fault Injection Attacks and Differential Fault Analysis have proven to be very dangerous as they are able to retrieve the secret information contained in cryptocircuits. In this sense, Trivium cipher has been shown to be vulnerable to this type of attack. This paper presents four different fault detection schemes to protect Trivium stream cipher implementations against fault injection attacks and differential fault analysis. These countermeasures are based on the introduction of hardware redundancy and signature analysis to detect fault injections during encryption or decryption operations. This prevents the attacker from having access to the faulty key stream and performing differential fault analysis. In order to verify the correct operation and the effectiveness of the presented schemes, an experimental system of non-invasive active attacks using the clock signal in FPGA has been designed. This system allows to know the fault coverage for both multiple and single faults. In addition, the results of area consumption, frequency degradation, and fault detection latency for FPGA and ASIC implementations are presented. The results show that all proposed countermeasures are able to provide a fault coverage above 79% and one of them reaches a coverage of 99.99%. It has been tested that the number of cycles for fault detection is always lower than the number of cycles needed to apply the differential fault analysis reported in the literature for the Trivium cipher.
Highlights
N OWADAYS the number of devices interconnected has grown exponentially, among other reasons, due to the great development of so-called internet of things (IoT)
OUR CONTRIBUTION This paper presents four different countermeasure proposals to significantly reduce the vulnerabilities of the Trivium cipher against active attacks by fault injection
COUNTERMEASURE ANALYSIS After describing the vulnerabilities of the Trivium cipher and the proposed countermeasures, we present the analysis of the resources they require for FPGA and ASIC technologie and the fault coverage they provide
Summary
N OWADAYS the number of devices interconnected has grown exponentially, among other reasons, due to the great development of so-called internet of things (IoT). Different DFA techniques have been reported in the literature in a satisfactory and effective way [8]–[13], showing the possibilities of endangering the security of the data exchanged when this cipher is implemented as protection These theoretical works, together with the experimental attacks presented in [14] and [15], have shown that this cipher must be protected to minimize its vulnerabilities against malicious attacks. OUR CONTRIBUTION This paper presents four different countermeasure proposals to significantly reduce the vulnerabilities of the Trivium cipher against active attacks by fault injection These countermeasures are: a total hardware redundancy, the use of LFSR as a signature generator, feedback protection using XOR gates, and the combination of the LFSR signature scheme and feedback protection scheme.
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