Analysis and Detection of Errors in KECCAK Hardware Implementation

Abstract

The third family Secure Hash Algorithm cryptographic function, named KECCAK, is implemented in cryptographic circuits to assure high security level to any system which necessitates hashing as the generation of random numbers and the data integrity checking. One of the most efficient physical attacks against KECCAK hardware implementation is the fault attacks which can extract the secret data. Until today, a few KECCAK fault detection schemes against the fault attacks have been presented. In this paper, in order to provide a high level of security against fault attacks, we perform a detailed fault analysis to estimate the impact of fault attacks against the KECCAK implementation. We then propose an efficient error detection scheme based on the KECCAK architecture modification. For this reason, the round of KECCAK is divided into two half rounds and a KECCAK pipeline register is implemented between them. The proposed scheme is independent of the method the KECCAK is implemented. Thus, it can be applied to both the pipeline and iterative architectures.To evaluate the KECCAK detection scheme robustness against faults injection attacks, we perform fault injection attacks and we determined the fault detection capability; it is about 99.997%. We have modeled the KECCAK detection scheme using the VHDL hardware language and through hardware FPGA implementation, the FPGA results demonstrate that our scheme can efficiently secure the KECCAK implementation against fault attacks. It can be simply implemented with low complexity. In addition, the FPGA implementation performances prove the low slice area overhead and the high working frequency for the proposed KECCAK detection scheme.