Extra Transistors Research Articles

Novel six‐phase ring voltage controlled oscillator with wide frequency tuning range

SummaryThis paper presents more compatible three‐stage inverter‐based ring voltage controlled oscillators (VCOs) by modifying the current‐starved delay cell to oscillate with high tuning range. Unlike some ring structures in which extra transistors are used as current boosting to enhance the frequency tuning range, no extra elements are used in the proposed three‐stage VCOs for increasing the tuning range. Besides, a new method is introduced to couple two proposed ring VCOs for designing a six‐phase ring VCO. The coupling method can be generalized to some other ring VCOs to generate multiphase signals. The proposed circuits have wide frequency tuning ranges and show good noise performances. The proposed six‐phase VCO can oscillate from 1.62 GHz to 3.45 GHz, which illustrates 72.2% tuning range. The phase noise of the proposed VCO is −97.5 dBc/Hz at 1 MHz offset frequency. The circuit figure of merit is −181.5 dBc/Hz. The post‐layout simulation results of the proposed six‐phase VCO are provided based on the TSMC 0.18 μm CMOS process.

Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell

Content addressable memories (CAMs) are a promising category of computing-in-memory (CiM) elements that can perform highly parallel and efficient search operations for routers, pattern matching, and other data-intensive applications. Various magnetic tunnel junction (MTJ) based content addressable memory (CAM) designs have been proposed to realize zero standby power and high performance search. However, due to the relatively small tunnel magneto-resistance (TMR) ratio, MTJ based CAMs require extra transistors and differential MTJ branches to distinguish between the parallel and anti-parallel resistance states, resulting in significant area and energy overhead. In this paper, we propose a device-circuit co-design approach for an ultra-compact CAM design by only exploiting an 1T-1MTJ structure in each cell. We propose a 2-step search scheme to enable the parallel in-memory search operation across the proposed CAM array, and demonstrate the sufficient sensing margin of the array in a successful search operation. Evaluation results suggest that our proposed 1T-1MTJ based CAM design improves 179X/301X area efficiency compared with the state-of-the-art 15T-4MTJ/20T-6MTJ CAM design. Application benchmarking on hyperdimensional computing (HDC) inference shows a 54.6X/12.8X speedup compared with GPU/20T-6MTJ CAM based approaches.

A Novel 8T XNOR-SRAM: Computing-in-Memory Design for Binary/Ternary Deep Neural Networks

Deep neural networks (DNNs) and Convolutional neural networks (CNNs) have improved accuracy in many Artificial Intelligence (AI) applications. Some of these applications are recognition and detection tasks, such as speech recognition, facial recognition and object detection. On the other hand, CNN computation requires complex arithmetic and a lot of memory access time; thus, designing new hardware that would increase the efficiency and throughput without increasing the hardware cost is much more critical. This area in hardware design is very active and will continue to be in the near future. In this paper, we propose a novel 8T XNOR-SRAM design for Binary/Ternary DNNs (TBNs) directly supporting the XNOR-Network and the TBN DNNs. The proposed SRAM Computing-in-Memory (CIM) can operate in two modes, the first of which is the conventional 6T SRAM, and the second is the XNOR mode. By adding two extra transistors to the conventional 6T structure, our proposed CIM showed an improvement up to 98% for power consumption and 90% for delay compared to the existing state-of-the-art XNOR-CIM.

An improved cascode common-source LNA with inductive source degeneration for RF applications

This paper presents a novel structure to enhance the power gain (S21) of the conventional cascode common-source (CS) low-noise amplifier (LNA) with inductive source degeneration. The proposed LNA has an extra transistor and a capacitor in comparison with the conventional structure. The additive transistor significantly increases the S21 of the conventional cascode CS LNA with inductive source degeneration with the same DC power consumption (PDC), third-order input intercept point (IIP3), area, and slightly lower noise figure (NF). The utilized capacitor is used to improve the IIP3 of the proposed LNA. The power gain improvement of the proposed LNA has been validated by both theoretical analysis and extensive post-layout simulation results. The proposed and conventional LNAs have been designed in TSMC 180 nm CMOS technology. The post-layout simulation results of the proposed LNA are 2.42 dB NF, S21 of 15.55 dB, and 0.84 dBm IIP3 while consuming 3.2 mW from 1.2 V power supply. The simulated S21 of the proposed LNA is about 2.55 dB (34.2 %) larger than the conventional cascode LNA with the same other performance parameters. Also, the achieved figure-of-merit (FoM) of the proposed LNA is substantially larger than the conventional cascode CS LNA with inductive source degeneration.

6T and 8T SRAM Cell Simulation with Power Loss Analysis

Reducing the power consumption in a VLSI circuits is a prime concern now a days. Memory circuits play an important role in the design of electronic small power devices. Almost every digital systems is having memory as an important part in their design. The high speed circuits dissipate a considerable amount of power in a short time. In this paper conventional SRAM cell is modified little bit to reduce the dynamic power dissipation. The overall capacitance reduced by adding few extra transistors. Because of the fact that charging and the discharging of the bit lines consumes the most power , so 6T cell and 8T cell can be used to reduce the power by adding an extra number of transistors to the pull down path. In this paper 6T SRAM cell as well as 8T SRAM cell simulated and their performance compared in terms of power dissipation.

A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks

We propose a novel ultra-low-power, voltage-based compute-in-memory (CIM) design with a new single-ended 8T SRAM bit cell structure. Since the proposed SRAM bit cell uses a single bitline for CIM calculation with decoupled read and write operations, it supports a much higher energy efficiency. In addition, to separate read and write operations, the stack structure of the read unit minimizes leakage power consumption. Moreover, the proposed bit cell structure provides better read and write stability due to the isolated read path, write path and greater pull-up ratio. Compared to the state-of-the-art SRAM-CIM, our proposed SRAM-CIM does not require extra transistors for CIM vector-matrix multiplication. We implemented a 16 k (128 × 128) bit cell array for the computation of 128× neurons, and used 64× binary inputs (0 or 1) and 64 × 128 binary weights (−1 or +1) values for the binary neural networks (BNNs). Each row of the bit cell array corresponding to a single neuron consists of a total of 128 cells, 64× cells for dot-product and 64× replicas cells for ADC reference. Additionally, 64× replica cells consist of 32× cells for ADC reference and 32× cells for offset calibration. We used a row-by-row ADC for the quantized outputs of each neuron, which supports 1–7 bits of output for each neuron. The ADC uses the sweeping method using 32× duplicate bit cells, and the sweep cycle is set to 2N−1+1, where N is the number of output bits. The simulation is performed at room temperature (27 °C) using 45 nm technology via Synopsys Hspice, and all transistors in bitcells use the minimum size considering the area, power, and speed. The proposed SRAM-CIM has reduced power consumption for vector-matrix multiplication by 99.96% compared to the existing state-of-the-art SRAM-CIM. Furthermore, because of the decoupled reading unit from an internal node of latch, there is no feedback from the reading unit, with read static noise, and margin-free results.

An active CMOS optical receiver employing an inductor-less, low-noise and high-gain regulated cascode transimpedance amplifier

This paper deals with a high-gain, active, modified RGC transimpedance amplifier with low noise characteristic operating in a 2.5 ​Gb/s optical receiver. By adding an extra transistor to the booster amplifier of an RGC circuit, and manipulating the trade-off between the frequency bandwidth and transimpedance gain, the transimpedance gain of 60 ​dBΩ is obtained, which reduces the input referred noise and enlarges the SNR of the circuit, while, consumes 760 ​μW power using 65 ​nm CMOS process. The TIA stage, also, occupies a small area due to existence of only five transistors in its structure. The circuit is mathematically analyzed and related simulations justify its proper performance as not only a 2.5Gbps TIA, but also as a 5Gbps TIA. Finally, the presented TIA is followed by three stages of an NMOS-PMOS differential limiting amplifier to test its behavior as a complete 2.5 ​Gb/s optical receiver, which provides 85′704Ω gain with dissipating power of 5 ​mW.

Assessment on the Adequacy of Current Supply Testing Methods in CMOS Operational Amplifier

As the CMOS innovation is downsizing, spillage power has gotten one of the most basic structure worries for the chip fashioner. This paper proposes examination on the adequacy of current gracefully testing strategies in cmos operational amplifiers. In this work, a two phase operational amplifier is structured and faults are infused utilizing 250nm innovation. We will assess the viability of current checking systems in distinguishing Bridge and open deformities in CMOS operational amplifiers. We ought to assess the identification capacities by utilizing two current testing strategies. The principal strategy comprises the oversight of the transient flexible current (IDDT) and the subsequent procedure comprises the observing of quiet gracefully current (IDDQ).The most probable resistive and open defects are infused utilizing fault infusion extra transistors. Exhibitions of the CMOS operational amplifier are additionally assessed after each issue infusion. Spice stimulation ought to be done to compare about the proposed test systems and assess the best performing one. We ought to assess the recognition abilities by utilizing two current testing procedures. The primary system comprises the oversight of the transient gracefully current (IDDT) and the subsequent method comprises the checking of quiet flexibly current (IDDQ). The most probable resistive and open deformities are infused utilizing fault infusion extra transistors. Exhibitions of the CMOS operational amplifier are likewise assessed after each fault infusion. Flavor re-enactments ought to be done to look at the proposed test strategies and assess the best performing one.

Simulation of 6T and 8T SRAM Cell with Power Dissipation Analysis

Reducing the power consumption in a VLSI circuits is a prime concern now a days. Memory circuits plays an important role in the design of electronic small power devices. Almost every digital systems is having memory as an important part in their design. The high speed circuits dissipate a considerable amount of power in a short time. In this paper conventional SRAM cell is modified little bit to reduce the dynamic power dissipation. The overall capacitance reduced by adding few extra transistors. Because of the fact that charging and the discharging of the bit lines consumes the most power , so 6T cell and 8T cell can be used to reduce the power by adding an extra number of transistors to the pull down path. In this paper 6T SRAM cell as well as 8T SRAM cell simulated and their performance compared in terms of power dissipation.

TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS

Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess timing margin but suffer from the short-path (SP) issue where SPs must be padded to exceed the detection window. SP padding (SPP) is similar to, but severer than, hold time fixing. Thus, it incurs significant area overhead, especially when working in the near-threshold region. In this article, we propose a transmission gate-based SPP (TG-SPP) method, which uses only one transmission gate to extend an SP to the negative clock phase while keeping the critical paths unaffected. Compared with the two-phase latch way or the conventional padding with tens to hundreds of buffers in an SP, our method efficiently decreases the overhead. We develop transmission gate insertion rules and an automatic insertion flow to overcome the complicated intersection problem of short and critical paths. To further reduce the EDAC area overhead, we also propose a lightweight error detection latch that has only two extra transistors compared to a conventional 24-T flip-flop for the conventional way. We implement all the proposed techniques in an SHA-256 chip using the 28-nm CMOS process. Results show that our TG-SPP method achieves the same padding effect as the two-phase latch-based method while reducing both the glitch power and sequential area overhead by a factor of 6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> . The fabricated resilient chips are measured to achieve 55%–405% frequency improvement and 38.6%–69.4% power saving compared with the typical margined baseline at the near-threshold region.

Estimation of power and delay in CMOS circuits using LCT

&lt;p&gt;With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors(HTLCT). In this paper, we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The estimation of power and delay will be discussed using LCT’s and HTLCT’s&lt;/p&gt;

An Offset Readout Current Sensing Scheme for One-Resistor RRAM-Based Cross-Point Array

The uneven sneak-path currents in resistive random access memory (RRAM) severely constrain the array size. To overcome this issue, we propose an innovative readout scheme that can fully offset the sneak-path currents in one-resistor (1R) RRAM array. Furthermore, the bit cell resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cell</sub> ) in an RRAM array can be simply evaluated as the ratio of read voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">read</sub> ) to the sensed offset current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">offset</sub> ). Even under extreme device distribution, a 512×512 array size is still obtained. This is the largest array among simple 1R RRAM, without using a selector device or extra transistor.

Estimation of Power and Delay in CMOS Circuits using Leakage Control Transistor

Abstract With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors (HTLCT).In this paper; we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The proposed technique overcomes the limitations posed by the existing methods for leakage reductions an average leakage reductions is 82.5%.The estimation of power and delay will be discussed using LCT’s and HTLCT’s.

40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor

A 40-nm CMOS wideband high-IF receiver is presented in this paper. The low-noise transconductance amplifier (LNTA) uses dual noise cancellation in order to improve its noise figure. The LNTA has also a folded-cascode structure to increase its output impedance and prepare for a current-mode passive mixer. This structure is merged into the output stage of the LNTA, so there is no need for extra transistors. Additionally, a modified charge-sharing bandpass filter with cross-connected transconductors to boost Q-factor is proposed and discussed. The highest voltage gain achieved by the receiver (RX) is 30 dB. The RX noise figure is 3.3 dB at the maximum gain, while the IIP3 is −2.5 dBm at 1 GHz. The area of the receiver is very competitive for the wide band considered, merely 0.137 mm2. The RX and clock generation circuitry drain 25 mA from a 0.9-V supply.

New CMOS realization of high performance Voltage Differencing Inverting Buffered Amplifier and its filter application

This paper describes a high performance voltage differencing inverting buffered amplifier (VDIBA). The transconductance of the proposed circuit is enhanced by using positive feedback technique with only two extra transistors used in active load. Moreover, the bandwidth of proposed circuit is enhanced by using resistive compensation technique. The performance of proposed VDIBA is demonstrated by detailed frequency analysis. Furthermore, it is shown that the transconductance can be enhanced up to 4.61 mS at biasing current of 300 µA. In addition, a third order low pass filter is given as an application example to confirm the high performance of the proposed VDIBA. The proposed low pass filter operates at natural pole frequency of 15 MHz. The proposed VDIBA and its filter application are implemented using TSMC 90 nm CMOS technology in Cadence virtuoso schematic composer at ±0.6 V supply voltage.

A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation

The power budget is expected to limit the portion of the chip that we can power ON at the upcoming technology nodes. This problem, known as the utilization wall or dark silicon, is becoming increasingly serious. With the introduction of 3-D integrated circuits (ICs), it is likely to become more severe. Thus, how to take advantage of the extra transistors, made available by Moore’s law and the onset of 3-D ICs, within the power budget poses a significant challenge to system designers. To address this challenge, we propose a 3-D hybrid architecture consisting of a CPU layer with multiple cores, a field-programmable gate array (FPGA) layer, and a DRAM layer. The architecture is designed for low power without sacrificing performance. The FPGA layer is capable of supporting a large number of accelerators. It is placed adjacent to the CPU layer, with a communication mechanism that allows it to access CPU data caches directly. This enables fast switches between these two layers. This architecture reduces the power and energy significantly, at better or similar performance. This then alleviates the dark silicon problem by letting us power ON more components to achieve higher performance. We evaluate the proposed architecture through a new framework we have developed. Relative to the out-of-order CPU, the accelerators on the FPGA layer can reduce function-level power by $6.9\times $ and energy-delay product (EDP) by $7.2\times $ , and application-level power by $1.9\times $ and EDP by $2.2\times $ , while delivering similar performance. For the entire system, this translates to a 47.5% power reduction relative to a baseline system that consists of a CPU layer and a DRAM layer. This also translates to a 72.9% power reduction relative to an alternative system that consists of a CPU layer, an L3 cache layer, and a DRAM layer.

Two‐transistor and two‐magnetic‐tunnel‐junction multi‐level cell structured spin‐transfer torque magnetic random access memory with optimisations on power and reliability

A two-transistor and two-magnetic-tunnel-junction (MTJ) multi-level cell (MLC) structure of spin-transfer torque magnetic random access memory (STT-RAM) is proposed. Compared with the conventional one-transistor and two-magnetic-tunnel-junction MLC STT-RAMs, by adding an extra access transistor and adjusting the connection of the two MTJs, the extra write power consumption on the soft bit MTJ can be reduced, which will also have a benefit to the lifetime of the soft bit. Specifically, the simulation results show that more than 75% write power consumption on the soft bit can be wiped out, and the area cost caused by the extra access transistor is negligible.

Design and Analysis of High Frame Rate Capable Active Pixel Sensor by Using CNTFET Devices for Nanoelectronics

This paper presents a high frame rate capable Active Pixel Sensor (APS) using Carbon Nanotube Field Effect Transistor (CNTFET) instead of Complementary Metal Oxide Semiconductor (CMOS). Conventionally, the design of a single APS circuit is based on three transistors (3T) model. In order to achieve higher frame rate, one extra transistor with a column sensor circuit has been introduced in the proposed design to reduce the readout time. This study also concerns about the effect of transistor sizing, bias current, and moreover, the chiral vector of CNTFET. The power consumption and power delay product (PDP) are also investigated for specific sets of reset and row selector signal. Data for these studies were collected with the help of HSPICE software which were further plotted in OriginPro to analyze the optimal operation point of APS circuit. The bias current was also recorded for the readout transistor which is uniquely introduced in the proposed model for achieving better readout time. Hence, the main focus of this paper is to improve the frame rate by reducing the readout time. Results of the proposed CNTFET APS circuit are compared with the conventional CMOS APS circuit. The performance benchmarking shows that CNTFET APS cell significantly reduces readout time, PDP, and thus can achieve much higher frame rate than that of conventional CMOS APS cell.

HD2 reduction technique for single‐ended amplifier

A new technique for second harmonic distortion (HD2) reduction is presented. The proposed technique can be very useful for front-end receiver applications where single-ended high-gain, low-distortion amplifiers are required. The theoretical analysis and simulations of this scheme in which the second derivative of the current can be cancelled by using an extra transistor biased in the triode region in parallel to a MOSFET in saturation is presented. This technique is also robust to process variations as a result of the use of a tuning voltage in the proposed design. A 9 dB reduction in the magnitude of HD2 has been achieved with this technique compared with an amplifier of similar power consumption. This technique can be used in a design without significant impact on area, power or noise performance.

Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model

The relentless push in technology scaling driven by Moore's law has witnessed fantastic gains in the quantities of transistors available on chips. Computer architects have exploited the extra transistors by incorporating several computing cores within a single processor. Heterogeneous processing in particular has become a useful technique for dealing with ever-present power and memory restrictions. Yet, the scope and diversity of current heterogeneous designs remain bounded by the level of functional abstraction specified by conventional instruction-set architectures (ISAs). In this article, the authors demonstrate how the functional abstraction level determines the capability and variety of a processor's functional units and accelerators, thereby restricting its degree of heterogeneity. Combining current heterogeneous techniques with software abstraction concepts, the authors propose a new functional ISA (F-ISA), which raises the functional abstraction level of machine instructions. Using this model to complement existing architectures makes available a wider scope and diversity of functional units and accelerators in order to exploit the ever-increasing transistor densities. Greater heterogeneity can offer advances in terms of object data mapping and execution, resulting in potentially substantial latency, memory footprint, and power/performance gains.