Extra Transistors Research Articles

Static Differential NCL Gates: Toward Low Power

This brief proposes a new topology for implementing differential null convention logic gates. The new topology relies on the static implementation of conventional versions of such gates and uses a set of extra minimum-sized transistors to cut off connections to the power rails in specific nodes while the gate is switching. It shows that albeit the extra transistors adding cost in area, they enable solid savings in dynamic and static power and improve transition delays. Electrical simulation results for a Kogge-Stone adder case study led to savings of 67.3% in dynamic power, 61.9% in static power, 67.2% in energy per operation, and 8.9% in forward propagation delay, when compared with a state-of-the-art differential topology.

Circuit‐level design technique to mitigate impact of process, voltage and temperature variations in complementary metal‐oxide semiconductor full adder cells

Modern digital circuits are facing aggressive technology and voltage scaling under emerging technology generations. This study proposes a circuit-level technique to mitigate the adverse effects of process, voltage and temperature (PVT) variations on the design metrics of full adder (FA) cells under such ultra-deep sub-micron technology nodes. The proposed FA cells exhibit improved variability because of the use of inverting low voltage Schmitt trigger sub-circuits incorporated in the designs in place of inverters. The proposed circuits have been designed to operate in the near-threshold region, which offers a trade-off between performance and power consumption. The comparative analysis based on Monte Carlo simulations in a SPICE environment, using the 16-nm complementary metal-oxide semiconductor predictive technology model, demonstrates that the proposed technique is capable of mitigating the impact of PVT variations on major design metrics such as power, delay and power-delay product in FA cells. This improvement is achieved at the expense of two extra transistors for every replaced inverter in the FA cell.

Direct-Conversion X-Ray Detector with 50-µm High-Gain Pixel Amplifiers for Low-X-Ray-Dose Digital Mammography

This study proposes an active pixel sensor (APS) design for readout signal amplification to replace the traditional passive pixel sensor (PPS) design. The APS design adds only one extra thin-film transistor (TFT) amplifier, giving it the high signal sensitivity of the APS architecture and the high spatial resolution of the PPS architecture. The mobility of the amorphous silicon (a-Si) TFT is 0.56 cm2/Vs, the signal amplification of the APS circuit is more than 10×, the on/off current ratio is more than 107, and the leakage current is on the order of 1 fA. A 200-µm-thick layer of amorphous selenium (a-Se) as the X-ray photoconductor was deposited on the APS array with 160 × 160 pixels of various sizes, down to 50 µm. The 40-kVp X-ray spectra obtained with tube currents of 40 and 50 mA, respectively, were used for measuring the gray-level contrast induced by the X-rays. The experimental results show that the gray-level contrasts for the 50-µm pixels were 5.57 ± 0.89 and 13.19 ± 1.94 and those for the 70-µm pixels were 15.94 ± 2.98 and 24.19 ± 2.76 under 40-kVp X-ray exposure at 40 and 50 mA, respectively.

Reimagining Heterogeneous Computing: a Functional Instruction Set Architecture (F-ISA) Computing Model

The relentless push in technology scaling driven by Moore's law has witnessed fantastic gains in the quantities of transistors available on chips. Computer architects have exploited the extra transistors by incorporating several computing cores within a single processor. Heterogeneous processing in particular has become a useful technique for dealing with ever-present power and memory restrictions. Yet, the scope and diversity of current heterogeneous designs remain bounded by the level of functional abstraction specified by conventional instruction-set architectures (ISAs). In this article, the authors demonstrate how the functional abstraction level determines the capability and variety of a processor's functional units and accelerators, thereby restricting its degree of heterogeneity. Combining current heterogeneous techniques with software abstraction concepts, the authors propose a new functional ISA (F-ISA), which raises the functional abstraction level of machine instructions. Using this model to complement existing architectures makes available a wider scope and diversity of functional units and accelerators in order to exploit the ever-increasing transistor densities. Greater heterogeneity can offer advances in terms of object data mapping and execution, resulting in potentially substantial latency, memory footprint, and power/performance gains.

Output gating performance overhead elimination for scan test

Switching activity is much higher in test mode as compared to normal mode of operation which causes higher power dissipation, and this leads to several reliability issues. Output gating is proposed as a very effective low-power test technique, which is used to eliminate redundant switching activity in the combinational logic of circuit under test (CUT) during the shifting of test vectors in a scan chain. This method reduces the average power significantly, but it introduces performance overhead in normal mode of operation. In this work, a new output gating technique is proposed which eliminates redundant switching activity in combinational logic of CUT during shifting of test vectors without any negative impact on performance as compared to earlier proposed output gating techniques. The proposed design also improves the performance of the scan flop in functional mode with negligible area overhead incurred due to extra transistors. Experimental results show that our design has a more robust performance over wide range of capacitive load as compared to earlier designs.

A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation

Dynamic adaptation using Razor-based detection and correction of timing errors has demonstrated substantial improvements in performance and energy-efficiency in microprocessors. In this work, we apply Razor to hardware accelerators that find increasing application in System-on-Chip designs with high-performance requirements that must be delivered under stringent power budgets. We describe the implementation and silicon measurement results from a Razor-based hardware loop-accelerator (RZLA), implementing the Sobel edge-detection algorithm. Unlike in microprocessors, the RZLA pipeline is datapath-dominated with statically-scheduled control that has queue-based storage structures which are simply extended to support check-pointing and recovery. We exploit these characteristics typical of DSP and image-processing accelerators to implement Razor recovery in manner that is amenable to RTL validation and verification. We show a low-overhead pulsed-latch based Razor Flip-flop (RFF) architecture that adds only a single extra transistor on clock to minimize clock power overhead. The RFF is deployed in conjunction with a level-sensitive latch-insertion based algorithm to address the minimum-delay constraint present in all Razor systems. This algorithm enables the use of 50% of the clock period for timing speculation leading to robust error detection and correction across a wide dynamic voltage- and frequency-scaling range. Fabricated in 65 nm CMOS, the RZLA reclaims voltage margins to demonstrate 34% energy-efficiency improvements on a per-device basis and 33% overall, for the entire batch of devices at 1 GHz operation.

부유게이트에 지역전계강화 효과를 이용한 아날로그 어레이 설계

1.2 더블 폴리 부유게이트 트랜지스터로 구성된 아날로그 메모리가 CMOS 표준공정에서 제작되었다. 효율적인 프로그래밍을 위해 일반적인 아날로그 메모리에서 사용되었던 불필요한 초기 소거 동작을 제거하였으며 프로그래밍과 읽기의 경로를 동일하게 가져감으로서 읽기 동작 시에 발생하는 증폭기의 DC 오프셋 문제를 근본적으로 제거하였다. 어레이의 구성에서 특정 셀을 주변의 다른 셀들로부터 격리시키는 패스 트랜지스터 대신에 Vmid라는 별도의 전압을 사용하였다. 실험 결과 아날로그 메모리가 디지털 메모리의 6비트에 해당하는 정밀도를 보였으며 프로그래밍 시에 선택되지 않은 주변의 셀들에 간섭 효과가 없는 것으로 확인되었다. 마지막으로, 아날로그 어레이를 구성하는 셀은 특이한 모양의 인젝터 구조를 가지고 있으며, 이것은 아날로그 메모리가 특별한 공정 없이도 트랜지스터의 breakdown 전압 아래에서 프로그래밍 되도록 하였다. An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

One zero‐voltage‐switching three‐transistor push–pull converter

One three-transistor push–pull (TTPP) converter is proposed in this study. In this TTPP converter, an extra transistor is inserted between the input power supply and midpoint of two primary windings. On the secondary side, a saturable inductor and an extra freewheeling diode are employed. Adopting the proposed pulse-width modulation method for three power switches, two original transistors can achieve zero-voltage-switching (ZVS) easily in a wide range of load current, the extra transistor can also realise ZVS assisted by the saturable inductor. Each operation mode of the proposed TTPP converters is discussed in detail. The soft-switching conditions are explained. One 83.3 kHz, 800 W prototype has been built. Its peak efficiency reaches 94.87%. The experimental result is provided to verify the analysis.

A 3 Megapixel 100 Fps 2.8 $\mu$m Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers

This paper presents a 3 megapixel 100 fps 2.8 μm pixel pitch CMOS image sensor (CIS) layer with built-in self-test (BIST) for three-dimensional (3D) integrated imagers. A modular CIS sub-array is proposed with new readout and control scheme. It needs only one micro-bump (μbump) per sub-array, instead of per-pixel or per-column, to release the design rule restriction of the 3D stacking process. The proposed readout structure with in-pixel two-dimensional (2D) decoding function achieves high spatial resolution, without degrading the frame rate. A BIST circuit is also proposed to filter out unqualified CIS layer before chip stacking, improving the yield performance of the final 3D integrated imagers, without adding extra transistor in the pixel. A CIS chip with 16 × 8 sub-arrays and a pixel size of 2.8 × 2.8 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was fabricated in TSMC 0.18 μm CIS process. The experimental results demonstrate the successful parallel output images of 3 megapixels with 16 × 8 modules at 100 fps. This shows that the imaging resolution is expandable by the proposed modular sub-array design and is expected to achieve 100 fps at multi-mega imaging for high-speed HDTV camera applications.

Elimination of output gating performance overhead for critical paths in scan test

Excessive switching activity in test mode results in higher power dissipation than normal mode of operation and becoming a serious issue, in order to avoid reliability problems. Scanning of test vectors in test mode causes unnecessary switching in combinational block which can be reduced by gating methods. Gating the outputs of scan cells is a recently proposed very efficient low power test technique, which reduces the scan shift power significantly. However, the output gating techniques impacts the performance severely. In this paper, we propose a modified transistor level design of a scan flip-flop for critical paths, which eliminates the unnecessary switching in combinational circuit during shift phase of a scan-based test, without the impact on performance as in earlier scan flip-flop output gating schemes (Khatri and Ganeshan, 2008). The new scan flop design not only eliminates the performance overhead of output gating but also improves the performance of the scan flop by 32.84% (Khatri and Ganeshan, 2008) and 11.5% (Yang et al., 2008). The new flip-flop disables the output and uses an alternate path for shifting the test vectors. This approach have area overhead of six extra transistors but improves the overall performance of scan flip-flop, so this approach is better suited for critical paths. This also allows us to increase the shift frequency in designs where shift power dissipation puts upper bound on the frequency, and hence reduces test application time.

A superior-order curvature corrected bandgap reference with less sensitivity of mismatch

A superior-order curvature corrected bandgap reference (BGR) is proposed. The BGR features itself by adding only an extra NMOS transistor to a first-order BGR. The extra transistor generates a piecewise nonlinear corrected current to reduce its temperature coefficient (TC) and forms a negative feedback to decrease the variation of offset and TC caused by mismatch. Measurement result shows the proposed BGR achieves most optimal TC of 2.8ppm/°C in the temperature range of -40∼125°C. The variation of offset and TC among different samples are reduced by the negative feedback effectively.

On the analysis of bipolar transistor based chaotic circuits: case of a two-stage colpitts oscillator

We perform a systematic analysis of a system consisting of a two-stage Colpitts oscillator. This well-known chaotic oscillator is a modification of the standard Colpitts oscillator obtained by adding an extra transistor and a capacitor to the basic circuit. The two-stage Colpitts oscillator exhibits better spectral characteristics compared to a classical single-stage Colpitts oscillator. This interesting feature is suitable for chaos-based secure communication applications. We derive a smooth mathematical model (i.e., sets of nonlinear ordinary differential equations) to describe the dynamics of the system. The stability of the equilibrium states is carried out and conditions for the occurrence of Hopf bifurcations are obtained. The numerical exploration reveals various bifurcation scenarios including period-doubling and interior crisis transitions to chaos. The connection between the system parameters and various dynamical regimes is established with particular emphasis on the role of both bias (i.e., power supply) and damping on the dynamics of the oscillator. Such an approach is particularly interesting as the results obtained are very useful for design engineers. The real physical implementation (i.e., use of electronic components) of the oscillator is considered to validate the theoretical analysis through several comparisons between experimental and numerical results.

A proposed DG-FinFET based SRAM cell design with RadHard capabilities

The radiation induced soft errors have become one of the most important and challenging failure mechanisms in modern electronic devices. This paper proposes a new circuit level hardening technique for reduction of soft error failure rate in DG-FinFET (double gate FinFET) based static random access memory (SRAM). Analysis for 32 nm and 45 nm technology nodes is carried out. It is inferred from the paper that the proposed SRAM cell outperforms over DICE latch in terms of fault tolerance of external data and control lines, power dissipation and fast recovery when exposed to radiation for both the technology nodes. This is primarily due to the addition of extra transistors used to neutralize the effect of single event upset without affecting normal operations. Transistor count increase the area and write delay by 7% and 20% respectively over that of DICE latch. While read delay decreases by 14% for the proposed SRAM cell.

A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits

A novel signal transition detector design using as few as 8 transistors is presented. The proposed design cleverly exploits the property of a specific internal state transition to mitigate the voltage degradation problem by employing only one extra transistor. It is thus capable of supporting level intact output signals and eliminating DC power consumption in the trailing buffer. The proposed design, featuring low circuit complexity and low power consumption, is considered useful for applications in self-timed circuits. Simulation results show that, when compared with other pass transistor logic based counterpart designs, as much as 46% savings in power and 28% in area can be achieved by the proposed design.

Application of a low‐glitch current cell in 10‐bit CMOS current‐steering DAC

PurposeThe purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption.Design/methodology/approachA low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation.FindingsCompared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within 0.1 LSB and the maximum power consumption is 68 mW at the sampling frequency of 100 MHz.Originality/valueComparison with other conventional work indicates that the current cell proposed in this paper shows much better performance in terms of switching spike and glitch, which may come from the extra dummy transistor in cell and reduce the clock‐feedthrough effect.

Advances in Reversed Nested Miller Compensation

The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RN-MCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included.

Boxes: An Engineering Methodology for Calculating Soft Error Rates in SOI Integrated Circuits

A simple methodology is necessary to characterize the SEU behavior of large quantities of RAM cell types, latches, flip-flops, other logic cells, I/O cells, etc. Such a methodology, called "Boxes", is being used for the Honeywell S150 radiation-hard 0.15 mum partially-depleted SOI process. Using physics-based equations, this paper shows how to break up each critical transistor into several "boxes", each with its own dimensions and critical charge, for the purpose of calculating soft error rate (SER). The Boxes methodology also allows for calculation of SER due to an ion that must simultaneously strike two separated sensitive volumes in order to cause an upset. This can be the dominant upset mechanism for many types of cells such as certain hardened SRAM's and other cells that obtain radiation hardness via extra transistors (such as triple modular redundancy, the DICE latch, etc.). Boxes also predicts upsets that can occur when an ion strike pulls a circuit node below ground or above the positive power supply. The boxes methodology was applied to a 6 T non-hardened SRAM, a hardened SRAM, and a D-type flip-flop. The theoretical predictions correlated well with experimental vertical ion strike data

Low-power scan design using first-level supply gating

Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement the masking effect by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops. The supply gating transistor is turned off in the scan-in mode, essentially gating the supply. Adding an extra transistor in only one logic level renders significant advantages with respect to area, delay, and power overhead compared to existing methods, which use gating logic at the output of scan flip-flops. Moreover, the proposed gating technique allows a reduction in leakage power by input vector control during scan shifting. Simulation results on ISCAS89 benchmarks show an average improvement of 62% in area overhead, 101% in power overhead (in normal mode), and 94% in delay overhead, compared to the lowest cost existing method.

A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications

This paper analyzes the performance of vector-dominated regions of code in numerical and multimedia applications in a superscalar + vector architecture and compares it with an eight-way superscalar processor. The ability to split a program’s execution into scalar and vector regions allows us to show that (1) as expected, the vector unit is much better than the wide-issue superscalar at executing the vector-dominated regions of the code; (2) on the scalar regions, the eight-way superscalar, although better than a four-way superscalar, is clearly not worth the extra complexity in terms of extra transistors and potential cycle-time limitations. Overall, the vector-enhanced superscalar is from 6% to 303% better than an eight-way superscalar. We also present detailed data on the performance of the memory system, which is usually the key limiting factor when running numerical and multi-\break media applications. We evaluate two additional cache designs that try to alleviate problems created by non-unit stride memory references.

A Low-Noise, High-Gain Single-Ended Input Double-Balanced Mixer

A noble single-ended input, double-balanced mixer topology is proposed. The mixer adopts a transconductance stage that amplifies the input and then converts it into differential currents leading to overall performance advantage compared to prior CG(common-gate)-CS(common-source)-based transconductance-stage mixer topologies without requiring additional power dissipation or extra transistor. The key specifications are compared with those of reported similar topologies, based on simulations.