Extra Transistors Research Articles

Making the best of those extra transistors

A new world for transistors may be on the horizon. The days of directly implementing custom functionality in transistors, and hence of designers creating their own chips, may be fading away. Prefabricated programmable platforms, considered grossly inefficient just a decade ago, may prevail, leading to lower costs, faster time to market, lower power, and other benefits perhaps not even foreseeable today.

Comments on "Series resistance compensation in translinear circuits

For the original paper see ibid., vol. 45, no. 1, p. 91-94 (1998). The aforementioned paper concerns canceling ohmic resistance errors in translinear and other circuits that depend on the logarithmic V/sub BE/-to-I/sub c/ relation in bipolar transistors (BJT's). This is sometimes broadly called logarithm-conformance error or LCE. The author described a circuit method using extra transistors whose LCE mimicked and canceled that in a main circuit. The commenter points out that LCE correction is a long standing issue in BJT analog circuits, with various successful solutions in print for at least 25 years. Hence he claims that the correction method described by Opris is not new and it also has a context of related published past art.

Design of CMOS PSCD Circuits and Checkers forStuck‐At and Stuck‐On Faults

We present in this paper an approach to designing partially strongly code‐disjoint (PSCD) CMOS circuits and checkers, considering transistor stuck‐on faults in addition to gate‐level stuck‐at faults. Our design‐for‐testability (DFT) technique requires only a small number of extra transistors for monitoring abnormal static currents, coupled with a simple clocking scheme, to detect the stuck‐on faults concurrently. The DFT circuitry not only can detect the faults in the functional circuit but also can detect or tolerate faults in itself, making it a good candidate for checker design. Switch and circuit level simulations were performed on a sample circuit, and a sample 4‐out‐of‐8 code checker chip using the proposed technique has been designed, fabricated, and tested, showing the correctness of the method. Performance penalty is reduced by a novel BiCMOS checker circuit.

Tunable CMOS current-mode sinusoidal oscillatorwith inherent automaticamplitude control

A high frequency CMOS current-mode sinusoidal oscillator is proposed which uses the difference between the output currents of two simple unequal bandwidth lowpass filters to obtain a frequency selective bandpass function. High oscillation frequencies are possible since the signal currents pass through only NMOS transistors. Both the gains and the limiting of the amplitudes of the oscillating currents are inherent in the lowpass units without using any extra transistors.

Testable design of BiCMOS circuits for stuck-open fault detection using single patterns

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults. >

Totally self-checking CMOS circuit design for breaks and stuck-on faults

A technique for designing totally self-checking FCMOS circuits is presented. Two types of defects have been considered: breaks (caused by missing conducting material or extra insulating material) and transistor stuck-on faults. In order to make FCMOS circuits totally self-checking for all breaks and transistor stuck-on faults, only four extra transistors need to be added to the functional circuit. The additional circuitry is added in such a way that for any break or transistor stuck-on defect in the functional circuit, the outputs assume a value of 01 or 10, respectively. The output of the defect-free circuit will be 11 (00) when the input pattern applied to the circuit connects V/sub dd/(GND) to the output node.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 209 K-transistor ECL gate array with RAM

The authors describe a gate array with an ECL (emitter-coupled-logic) cell structure for implementing a high-density configurable RAM. A unit based on a variable size cell is modified to achieve such a RAM. Every unit has an extra transistor buried under the power bus to eliminate area penalty. One memory bit is constructed using one buried transistor plus three transistors in a unit. An n-p-n transistor and a tap resistor load cell are employed for structural matching with the logic gates. Since the read current is supplied directly from the V/sub CC/ bus instead of the word line, the transistor size of the word-line driver is minimized. The standby and read currents are 120 mu A and 800 mu A, respectively. The decoder, sense amplifiers, and word-line drivers are implemented by logic gates. RAM size can be varied by each unit row; the bit increment is 144. The process employs double-polysilicon self-aligned technology with a silicide-base electrode of TiSi/sub 2/ and triple-layer metallization. The features of the gate array are listed. >

CMOS open-fault detection in the presence of glitches and timing skews

A testable CMOS design technique in which some extra transistors are used in such a way that the CMOS gate is converted to a pseudo-nMOS/pMOS gate during testing is discussed. With the proposed design technique, CMOS open faults can be detected regardless of timing skews/delays, glitches, or charge sharing among the internal nodes. The major advantage of the proposed testable design technique is that it allows the use of a single test vector to detect a stuck-open fault. This significantly reduces the complexity of test generation and the time consumed for testing. The design procedure is simple and all the classical algorithms and automatic test-pattern-generating programs can be used to generate tests for circuits designed according to this technique. Even random testing techniques can be used efficiently to detect the open faults in these CMOS circuits. >

CMOS latchup modelling: a new approach

Abstract In this paper, a new lumped element latchup model which includes two extra bipolar transistors is proposed. The divergence between the results of the conventional and the proposed model is explained in terms of the circuit parameters. The output behaviour of CMOS latchup and the output latchup mode are discussed in connection with the proposed model and the predictions of the model are compared to the results of the conventional model using SPICE.