Abstract
We present in this paper an approach to designing partially strongly code‐disjoint (PSCD) CMOS circuits and checkers, considering transistor stuck‐on faults in addition to gate‐level stuck‐at faults. Our design‐for‐testability (DFT) technique requires only a small number of extra transistors for monitoring abnormal static currents, coupled with a simple clocking scheme, to detect the stuck‐on faults concurrently. The DFT circuitry not only can detect the faults in the functional circuit but also can detect or tolerate faults in itself, making it a good candidate for checker design. Switch and circuit level simulations were performed on a sample circuit, and a sample 4‐out‐of‐8 code checker chip using the proposed technique has been designed, fabricated, and tested, showing the correctness of the method. Performance penalty is reduced by a novel BiCMOS checker circuit.
Highlights
Investigation of totally self-checking (TSC) checkers dates back at least as far as 1968 [1] Classical gate-level single stuck-at fault model has been adopted by most researchers ever since
We first review a novel scheme of detecting transistor stuck-on faults which was proposed by Favalli, et a/. [19]
The circuit is modified to fulfill the requirement of concurrent error detection, and is called the analogfault detection (AFD)
Summary
Investigation of totally self-checking (TSC) checkers dates back at least as far as 1968 [1] Classical gate-level single stuck-at fault model has been adopted by most researchers ever since. Results have been presented on the design of CMOS circuits in which single stuck-open faults are detectable by robust tests[3]. If the checkers are realized using only CMOS domino gates, they will remain self-testing for all single stuck-at and stuck-open faults, and most stuck-on faults[4]. In a system where self-checking circuits and checkers are implemented for concurrent error detection, off-chip current monitoring is not practical. A simple inverter chain and a 4-out-of-8 code checker using the proposed technique are presented to justify our concurrent detection approach. Performance penalty reduction by the BiCMOS technology has been proposed
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