A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits

Abstract

A novel signal transition detector design using as few as 8 transistors is presented. The proposed design cleverly exploits the property of a specific internal state transition to mitigate the voltage degradation problem by employing only one extra transistor. It is thus capable of supporting level intact output signals and eliminating DC power consumption in the trailing buffer. The proposed design, featuring low circuit complexity and low power consumption, is considered useful for applications in self-timed circuits. Simulation results show that, when compared with other pass transistor logic based counterpart designs, as much as 46% savings in power and 28% in area can be achieved by the proposed design.