Abstract
A two-transistor and two-magnetic-tunnel-junction (MTJ) multi-level cell (MLC) structure of spin-transfer torque magnetic random access memory (STT-RAM) is proposed. Compared with the conventional one-transistor and two-magnetic-tunnel-junction MLC STT-RAMs, by adding an extra access transistor and adjusting the connection of the two MTJs, the extra write power consumption on the soft bit MTJ can be reduced, which will also have a benefit to the lifetime of the soft bit. Specifically, the simulation results show that more than 75% write power consumption on the soft bit can be wiped out, and the area cost caused by the extra access transistor is negligible.
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