Extended Drain MOS Research Articles

Electrical characteristics and optimization of extended-drain MOS transistor with dual-workfunction-gate for mixed-signal applications

This paper presents the electrical characteristics of high-voltage (HV) extended-drain MOS (EDMOS) field-effect transistor with dual-workfunction-gate (DWFG) to enhance the device performance and device optimization for mixed-signal applications. For n-channel DWFG EDMOS device fabrication, the polycrystalline-silicon (poly-Si) gate on the source and drain side were doped by p+ and n+ ion implantation, respectively. The DWFG device with shorter p+ poly-Si gate length showed lower on-resistance (RON) characteristics compared to the conventional device. Therefore, the DWFG device with shorter p+ poly-Si gate length is suitable for switching applications. On the other hand, the best improvements in the drain conductance (gds) and intrinsic voltage gain (AV), which is important parameters of analog circuits, were shown in the DWFG device with identical n+ and p+ poly-Si gate length.

Hot-Carrier-Induced Forward and Reverse Saturation Current Degradations for the n-Type Symmetric EDMOS Transistor

In this letter, hot-carrier-induced degradations of forward and reverse saturation current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) under the worst stress condition are experimentally investigated for the n-type symmetric extended drain MOS (ns-EDMOS) transistor. It shows that the degradation of the reverse I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> is much larger than that of the forward I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> . Further experiments demonstrate that the phenomenon mainly results from different influences of the substrate current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> ) degradation upon the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> degradation between the forward and the reverse operational conditions. At forward operational condition, the generated acceptor-like interface states will capture the electrons and enhance the Kirk effect. Subsequently, the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> degradation is partially neutralized by the increase of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> . However, for the reverse operational condition, the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> shift aggravates the degradation of the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> . Therefore, instead of forward I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> , reverse I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> should be selected as the critical parameter to evaluate hot-carrier lifetime of the ns-EDMOS device.

Linear Drain Current Degradation of FG-pLEDMOS Transistor Under Pulse Gate Stress With Different Rising and Falling Edges

Linear drain current degradation of a field-gate p-channel lateral extended drain MOS (FG-pLEDMOS) transistor for different ac hot-carrier stress conditions has been experimentally investigated in this paper. It is noted that hot-carrier degradation strongly depends on the time of the rising and falling edges of the gate signal pulse. Faster rising and falling edges of the gate pulse will induce more serious hot-carrier degradation. Moreover, the experimental results reveal that the falling edges of the gate pulse show more distinct influence upon hot-carrier degradation than that of the rising edges. In this way, the pulse gate stress with fast falling edges should be considered for evaluating the hot-carrier-induced lifetime of a laterally diffused MOS working with fast gate signal pulse edges.

High‐voltage EDMOS transistor with dual work function gate

A high-voltage extended drain MOS (EDMOS) transistor with a dual work function gate (DWFG) is discussed. This device enhances device performance by modifying the electric field in the channel. For DWFG EDMOS device fabrication, the polycrystalline silicon gates on the source and drain sides are doped by p + and n + ion implantation, respectively. Experimental results from the fabricated DWFG EDMOS devices show improved transconductance (g m), drain conductance (g ds) and specific on-resistance (R ON) characteristics without breakdown voltage reduction.

Off-State Stress Degradation Analysis and Optimization for the High-Voltage SOI-pLEDMOS With Thick Gate Oxide

In this paper, the off-state stress degradation for the high-voltage p-type lateral extended drain MOS (pLEDMOS) based on the silicon-on-insulator (SoI) substrate with the thick gate oxide has been investigated experimentally. It shows that, during the stress, there are interface states and negative oxide-trapped charges at the polygate terminal region, but the negative oxide-trapped charges are identified to be the main degradation mechanism. In addition, because the difference of the depletion widths leads to different current paths depth under two monitor conditions, it has been observed that the degradation of the saturation drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dsat</sub> ) is always much more serious than that of the linear drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dlin</sub> ). Finally, a novel SoI-pLEDMOS transistor with a reversed doped HV-N-well has been presented to optimize the off-state degradation.

An Accurate and Robust Compact Model for High-Voltage MOS IC Simulation

This paper presents an accurate and robust compact model for high-voltage MOS (HV-MOS) transistors for high-voltage IC simulation. This model describes the extended-drain MOS and lateral double-diffused HV-MOS effects such as quasi-saturation, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> reduction, self-heating, impact ionization, output conductance, and charge/capacitance effects accurately. In addition, the quasi-saturation effects are, for the first time, illustrated with a simple mathematic formulation. This model is developed with BSIM4 as the base and validated extensively with technology computer-aided design and measurement for wide ranges of power supplies and operating temperatures.

A novel pLEDMOS device with large current capability and high reliability for PDP scan driver IC

A novel p-type lateral extended drain MOS (pLEDMOS) based on an SOI substrate has been presented for plasma display panels scan driver IC. By introducing a reversed doped high-voltage-Nwell that fabricated by the special SOI process, both the current capability and off-state breakdown voltage (BV) of the device are optimized well. The saturation current density over 0.6 mA µm−1 and the BV over 210 V for the novel pLEDMOS are achieved by using a 0.5 µm SOI CMOS process. Moreover, the hot-carrier degradation has also been improved compared with the conventional device.

Reliability investigations and improvements of the pLEDMOS for PDP data driver ICs

In this paper, the p-type lateral extended drain MOS (pLEDMOS) transistor with thick gate oxide for plasma display panel (PDP) data driver ICs is developed. The following reliability issues have been discussed in detail: (1) hot-carrier degradation, (2) the contradiction between the parasitic bipolar junction transistor (BJT) punch-through phenomenon and the impurity segregation effect, (3) surface damage caused by the long-time diffusion process under high-temperature conditions, (4) creep behavior of the breakdown voltage and (5) the Kirk effect due to the high working current density. The improved methods for solving these reliability problems by optimizing the process and device architecture are also presented. The methods have also been verified by the technology computer-aided design (TCAD) simulations and experimental results.

Devices’ optimization against hot-carrier degradation in high voltage pLEDMOS transistor

The degradations of p-type lateral extended drain MOS transistors with thick gate oxide are experimentally investigated. To decrease the hot-carrier degradation, two methods are proposed to optimize the drift region without additional processes. The novel structure is with a low doped boundary of the drift region and a drift region implanted at intervals by multi-windows, which will be helpful in reducing the electric field, reducing the degradations of electrical parameters correspondingly. The effects have been detailed analyzed by the CP measurements and TCAD simulations. Out of the simulations results, the length of the low doped boundary and the space between the doping windows of the sub-drifts are discussed, and their effects on the degradation induced by hot carriers has been investigated in detailed. An optimization structure is proposed for the first time.

Layout and process hot carrier optimization of HV-nLEDMOS transistor

Two layout and process key parameters for improving high voltage nLEDMOS (n-type lateral extended drain MOS) transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carrier degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.

On-Resistance Degradations for Different Stress Conditions in High-Voltage pLEDMOS Transistor With Thick Gate Oxide

The different on-resistance degradations of the p-type lateral extended drain MOS (pLEDMOS) transistor with thick gate oxide for different hot carrier stress conditions have been experimentally investigated for the first time. The difference results from the interface trap generation and the hot electron injection and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor, which has been analyzed in detail using the MEDICI simulator.

A High Voltage Line Driver for Subscriber Loop Interfaces in a Low Voltage Submicron BiCMOS Technology

This paper presents a 30 V line driver for short loop subscriber line interface circuit applications. The high voltage line drivers was implemented in a low-voltage 0.8 μm BiCMOS process using 30 V extended-drain MOS transistors, fully compatible with the low voltage technology. Using a Quasi-Current Mirror architecture for the output stage, the line driver is capable of delivering more than 30 mA current into the lines with an idle current as low as 1 mA, satisfying the short loop requirements. With less than 0.24 mm^2 area, the circuit can be easily integrated with low-voltage circuitry on a single chip.