Evolvable Hardware System Research Articles

A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays

Brain-inspired computing takes inspiration from the brain to create energy-efficient hardware systems for information processing, capable of performing highly sophisticated tasks. Systems built with emerging electronics, such as memristive devices, can achieve gains in speed and energy by mimicking the distributed topology of the brain. In this work, a brain-inspired hardware architecture for evolutionary algorithms is proposed based on memristive arrays, which can realize sparse and approximate computing as a result of the parallel analog computing characteristic of the memristive arrays. On this basis, an efficient evolvable brain-inspired hardware system is implemented. We experimentally show that the approach can offer at least a four orders of magnitude speed improvement. We also use experimentally grounded simulations to explore fault tolerance and different parameter settings in the implemented hardware system. The experimental results show that the evolvable hardware system, implemented based on the proposed hardware architecture, can continuously evolve toward a better system even if there are failures or parameter changes in the memristive arrays, demonstrating that the proposed hardware architecture has good adaptability and fault tolerance.

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs

Current edge computing systems are deployed in highly complex application scenarios with dynamically changing requirements. In order to provide the expected performance and energy efficiency values in these situations, the use of heterogeneous hardware/software platforms at the edge has become widespread. However, these computing platforms still suffer from the lack of unified software-driven programming models to efficiently deploy multi-purpose hardware-accelerated solutions. In parallel, edge computing systems also face another huge challenge: operating under multiple conditions that were not taken into account during any of the design stages. Moreover, these conditions may change over time, forcing self-adaptation mechanisms to become a must. This paper presents an integrated architecture to exploit hardware-accelerated data-parallel models and transparent hardware/software multithreading. In particular, the proposed architecture leverages the ARTICo <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> framework and ReconOS to allow developers to select the most suitable programming model to deploy their edge computing applications onto run-time reconfigurable hardware devices. An evolvable hardware system is used as an additional architectural component during validation, providing support for continuous lifelong learning in smart edge computing scenarios. In particular, the proposed setup exhibits online learning capabilities that include learning by imitation from software-based reference algorithms. Experimental results show the benefits of the proposed approach, exposing different run-time tradeoffs (e.g., computing performance versus functional correctness of the evolved solutions), and highlighting the benefits of using scalable data-parallel models to perform circuit evolution under dynamically changing application scenarios.

Accelerating the evolution of a systolic array-based evolvable hardware system

Evolvable hardware is a type of hardware that is able to adapt to different problems by going through a previous training stage which uses an evolutionary algorithm to find an optimized configuration. This configuration can be achieved through dynamic partial reconfiguration of an FPGA. Having a short time for the training stage is critical for the system to be able to adapt to changing conditions in real time. However, one of the problems of evolvable hardware based on dynamic partial reconfiguration is its long evolution time, mostly due to its slow reconfiguration speed. This can make such systems unsuitable for applications which require adaptation in a few seconds. Nevertheless, different reconfiguration and evolution techniques can substantially reduce the time taken by an evolvable hardware system to evolve for a specific problem.In this article, a system initially able to evolve in 8 minutes is optimized using multiple techniques (reconfiguration methodology, evolutionary algorithm optimization, and parallelization) so that it is able to obtain similar results in less than 2 s, achieving a speedup of near 300 times. Extensive experimental results prove the benefits of such techniques.

Comparing three online evolvable hardware implementations of a classification system

In this paper, we present three implementations of an online evolvable hardware classifier of sonar signals on a 28 nm process technology FPGA, and compare their features using the most relevant metrics in the design of hardware: area, timing, power consumption, energy consumption, and performance. The three implementations are: one full-hardware implementation in which all the modules of the evolvable hardware system, the evaluation module and the Evolutionary Algorithm have been implemented on the ZedBoard™ Zynq® Evaluation Kit (XC7-Z020 ELQ484-1); and two hardware/software implementations in which the Evolutionary Algorithm has been implemented in software and run on two different processors: Zynq® XC7-Z020 and MicroBlaze™. Additionally, each processor-based implementation has been tested at several processor speeds. The results prove that the full-hardware implementation always performs better than the hardware/software implementations by a considerable margin: up to $$\times \,7.74$$ faster than MicroBlaze, between $$\times \,1.39$$ and $$\times \,2.11$$ faster that Zynq, and $$\times \,0.198$$ lower power consumption. However, the hardware/software implementations have the advantage of being more flexible for testing different options during the design phase. These figures can be used as a guideline to determine the best use for each kind of implementation.

A projection-based decomposition for the scalability of evolvable hardware

Scalability is a main and urgent problem in evolvable hardware (EHW) field. For the design of large circuits, an EHW method with a decomposition strategy is able to successfully find a solution, but requires a large complexity and evolution time. This study aims to optimize the decomposition on large-scale circuits so that it provides a solution for the EHW method to scalability and improves the efficiency. This paper proposes a projection-based decomposition (PD), together with Cartesian genetic programming (CGP) as an EHW system namely PD-CGP, to design relatively large circuits. PD gradually decomposes a Boolean function by adaptively projecting it onto the property of variables, which makes the complexity and number of sub-logic blocks minimized. CGP employs an evolutionary strategy to search for the simple and compact solutions of these sub-blocks. The benchmark circuits from the MCNC library, $$n$$n-parity circuits, and arithmetic circuits are used in the experiment to prove the ability of PD-CGP in solving scalability and efficiency. The results illustrate that PD-CGP is superior to 3SD-ES in evolving large circuits in terms of complexity reduction. PD-CGP also outperforms GDD+GA in evolving relatively large arithmetic circuits. Additionally, PD-CGP successfully evolves larger $$n$$n-even-parity and arithmetic circuits, which have not done by other approaches.

Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing

This paper presents an evolvable hardware system, fully contained in an FPGA, which is capable of autonomously generating digital processing circuits, implemented on an array of processing elements (PEs). Candidate circuits are generated by an embedded evolutionary algorithm and implemented by means of dynamic partial reconfiguration, enabling evaluation in the final hardware. The PE array follows a systolic approach, and PEs do not contain extra logic such as path multiplexers or unused logic, so array performance is high. Hardware evaluation in the target device and the fast reconfiguration engine used yield smaller reconfiguration than evaluation times. This means that the complete evaluation cycle is faster than software-based approaches and previous evolvable digital systems. The selected application is digital image filtering and edge detection. The evolved filters yield better quality than classic linear and nonlinear filters using mean absolute error as standard comparison metric. Results do not only show better circuit adaptation to different noise types and intensities, but also a nondegrading filtering behavior. This means they may be run iteratively to enhance filtering quality. These properties are even kept for high noise levels (40 percent). The system as a whole is a step toward fully autonomous, adaptive systems.

Le syndrome de Pancoast et Tobias malin (à propos de 40 cas)

A group-testing-based fault resolution is incorporated into SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) to provide an evolvable hardware system with self-healing and self-organizing properties. The proposed approach employs adaptive group testing techniques to autonomously maintain FPGA resource viability information as an organic means of transient and permanent fault resolution. Reconfigurability of the SRAM-based FPGA is leveraged to locate faulty logic resources which are successively excluded by group testing using alternate device configurations. This simplifies the system architect’s role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance vs. availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an observer–controller model. The proposed group testing method operates on the output response produced for real-time operational inputs, which eliminates the need for dedicated test vectors. The proposed system was demonstrated using a Data Encryption Standard (DES) core on 4-input and 6-input LUT-based Xilinx FPGA models. With a single simulated stuck-at fault, the system identifies a completely validated replacement configuration within a few test stages. Results also include approaches for optimizing group size, resource redundancy, and availability. The approach demonstrates a readily-implemented yet robust organic hardware application that features a high degree of autonomous self-control.

On the Evolution of Hardware Circuits via Reconfigurable Architectures

Traditionally, hardware circuits are realized according to techniques that follow the classical phases of design and testing. A completely new approach in the creation of hardware circuits has been proposed---the Evolvable Hardware (EHW) paradigm, which bases the circuit synthesis on a goal-oriented evolutionary process inspired by biological evolution in Nature. FPGA-based approaches have emerged as the main architectural solution to implement EHW systems. Various EHW systems have been proposed by researchers but most of them, being based on outdated chips, do not take advantage of the interesting features introduced in newer FPGAs. This article describes a project named Hardware Evolution over Reconfigurable Architectures (HERA), which aims at creating a complete and performance-oriented framework for the evolution of digital circuits, leveraging the reconfiguration technology available in FPGAs. The project is described from its birth to its current state, presenting its evolutionary technique tailored for FPGA-based circuits and the most recent enhancements to improve the scalability with respect to problem size. The developed EHW system outperforms the state of the art, proving its effectiveness in evolving both standard benchmarks and more complex real-world applications.

Self-healing reconfigurable logic using autonomous group testing

A group-testing-based fault resolution is incorporated into SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) to provide an evolvable hardware system with self-healing and self-organizing properties. The proposed approach employs adaptive group testing techniques to autonomously maintain FPGA resource viability information as an organic means of transient and permanent fault resolution. Reconfigurability of the SRAM-based FPGA is leveraged to locate faulty logic resources which are successively excluded by group testing using alternate device configurations. This simplifies the system architect’s role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance vs. availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an observer–controller model. The proposed group testing method operates on the output response produced for real-time operational inputs, which eliminates the need for dedicated test vectors. The proposed system was demonstrated using a Data Encryption Standard (DES) core on 4-input and 6-input LUT-based Xilinx FPGA models. With a single simulated stuck-at fault, the system identifies a completely validated replacement configuration within a few test stages. Results also include approaches for optimizing group size, resource redundancy, and availability. The approach demonstrates a readily-implemented yet robust organic hardware application that features a high degree of autonomous self-control.

Evolvable Hardware System Based on FPGA

Evolvable Hardware System Based on FPGA

A three-step decomposition method for the evolutionary design of sequential logic circuits

Evolvable hardware (EHW) refers to an automatic circuit design approach, which employs evolutionary algorithms (EAs) to generate the configurations of the programmable devices. The scalability is one of the main obstacles preventing EHW from being applied to real-world applications. Several techniques have been proposed to overcome the scalability problem. One of them is to decompose the whole circuit into several small evolvable sub-circuits. However, current techniques for scalability are mainly used to evolve combinational logic circuits. In this paper, in order to decompose a sequential logic circuit, the state decomposition, output decomposition and input decomposition are united as a three-step decomposition method (3SD). A novel extrinsic EHW system, namely 3SD---ES, which combines the 3SD method with the (μ, ?) ES (evolution strategy), is proposed, and is used for the evolutionary designing of larger sequential logic circuits. The proposed extrinsic EHW system is tested extensively on sequential logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The results demonstrate that 3SD---ES has much better performance in terms of scalability. It enables the evolutionary designing of larger sequential circuits than have ever been evolved before.

Ubiquitous evolvable hardware system for heart disease diagnosis applications

This paper presents a stand-alone ubiquitous evolvable hardware (u-EHW) system that is effective for automated heart disease diagnosis applications. The proposed u-EHW system consists of a novel reconfigurable evolvable hardware (rEHW) chip, an evolvable embedded processor, and a hand-held terminal. Through adaptable reconfiguration of the filter components, the proposed u-EHW system can effectively remove various types of noise from ECG signals. Filtered signals are sent to a PDA for automated heart disease diagnosis, and diagnosis results with filtered signals are sent to the medical doctor's computer for final decision. The rEHW chip features FIR filter evolution capability, which is realised using a genetic algorithm. A parallel genetic algorithm evolves FIR filters to find the optimal filter combination configuration, associated parameters, and the structure of the feature space adaptively to noisy environments for adaptive signal processing. The embedded processor implements feature extraction and a classifier for each group of signal types. The proposed u-EHW system is a promising solution for various applications such as DSPs, communications, and ubiquitous healthcare systems.

Generalized Disjunction Decomposition for Evolvable Hardware

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + lambda) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided.

Chose the Right Mutation Rate for Better Evolve Combinational Logic Circuits

Evolvable hardware (EHW) is a developing field that applies evolutionary algorithm (EA) to automatically design circuits, antennas, robot controllers etc. A lot of research has been done in this area several different EAs have been introduced to tackle numerous problems, as scalability, evolvability etc. However every time a specific EA is chosen for solving a particular task, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade the selection of the right parameters for the EA's components for solving different test- problems has been investigated. In this paper the behaviour of mutation rate for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies the number of inputs of each logic gates, the functionality (for example from AND to NOR) and the connectivity between logic gates. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates for the evolved circuits. The experimental results found provide the behaviour of the mutation rate during evolution for the design and optimization of simple logic circuits. The experimental results propose the best mutation rate to be used for designing combinational logic circuits. The research presented is particular important for those who would like to implement a dynamic mutation rate inside the evolutionary algorithm for evolving digital circuits. The researches on the mutation rate during the last 40 years are also summarized.

Mutation Rate for Evolvable Hardware

Evolvable hardware (EHW) refers to a self- reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). A lot of research has been done in this area several different EA have been introduced. Every time a specific EA is chosen for solving a particular problem, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade a lot of research has been carried out in order to identify the best parameters for the EA's components for different test-problems. However different researchers propose different solutions. In this paper the behaviour of mutation rate on (1+λ) evolution strategy (ES) for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies values of the logic cell inputs, the cell type (for example from AND to NOR) and the circuit output. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates used for the evolved circuits. The experimental results found provide the behaviour of the mutation rate to be used during evolution for the design and optimization of logic circuits. The researches on the best mutation rate during the last 40 years are also summarized. Keywords—Evolvable hardware, mutation rate, evolutionary computation, design of logic circuit.