ESD Protection Scheme Research Articles

Towards efficient ESD protection strategies for advanced 3D systems-on-chip

Towards efficient ESD protection strategies for advanced 3D systems-on-chip

ESD protection for negative charge pump (CP) using CP internal switches

The standard ESD protection schemes are not very reliable for negative charge pump used in Class G power amplifiers. This work presents a novel ESD protection scheme using internal charge pump switches as ESD clamps. Transmission line pulsing (TLP) measurements show that an elevated level of ESD protection can be achieved with this scheme.

양 방향성과 높은 홀딩전압을 갖는 사이리스터 기반 Whole-Chip ESD 보호회로

We have investigated the electrical characteristics of SCR(Silicon Controlled Rectifier)-based ESD power clamp circuit with high holding voltage and dual-directional ESD protection cells for a whole-chip ESD protection. The measurement results indicate that the dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V). Also A dual-directional ESD protection circuit is designed for I/O ESD protection application. The trigger voltage and the holding voltage are measured to 5V and 3V respectively. In comparison with typical ESD protection schemes for whole-chip ESD protection, this ESD protection device can provide an effective protection for ICs against ESD pulses in the two opposite directions, so this design scheme for whole-chip ESD protection can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. Finally, a whole-chip ESD protection can be applied to 2.5~3.3V VDD applications. The robustness of the novel ESD protection cells are measured to HBM 8kV and MM 400V.

Investigation of ESD protection strategy in high voltage Bipolar–CMOS–DMOS process

This paper presents device optimization and physical analysis based on gate-grounded NMOS (GGNMOS) and n-channel lateral DMOS (nLDMOS) devices manufactured in a 0.35μm 5V/30V high-voltage BCD process. The multiple body pick-up technique has been investigated in detail for the GGNMOS, and the robustness and effectiveness of the LDMOS device is optimized by tuning the drain contact to gate space (DCGS) and increasing the body resistance. Finally, the trigger voltage walk-in effect is observed for the nLDMOS device and is studied by comprehensive simulation and TLP tests.

A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices

For three fundamental input-protection schemes suitable for high-frequency CMOS ICs, which utilize protection devices such as NMOS transistors, thyristors, and diodes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit model of input HBM test environments for CMOS chips equipped with input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the peak voltage developed in the later stage of discharge, which corresponds to the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain strength and weakness of each protection scheme as an input ESD protection circuit for high-frequency ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits

SUMMARY An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-μm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be codesigned with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.

ESD issues in advanced CMOS bulk and FinFET technologies: Processing, protection devices and circuit strategies

The ESD performance of several CMOS bulk and SOI technologies is reviewed. The ESD area-efficiency of FinFETs is put in relation to bulk and SOI. CMOS bulk technologies have improved over the past generations owing to the possibility of reduced ESD layout dimensions. While having observed It2 values of less than 2 mA/μm 2 in 130 nm technology, we are able to obtain almost 4 mA/μm 2 in 45 nm. Downscaling will shift the challenge for a robust ESD design from the ESD protection device in the IO cell to the metal routing and voltage clamping in the supply tree. This will increase cost and effort for ESD protection of modern IC’s in spite of improvement in It2. For FinFET technologies, the influence of device layout, electrical operation modes and processing is discussed. The initially extremely low ESD values of FinFETs have been strongly improved by overall process maturity and added process features. The ESD levels of FinFET technologies are now scalable up to the levels compliant with full IC design constraints. While the area-performance is still about two times lower than in bulk CMOS, it is much better than anticipated earlier. In light of the challenges ahead for technology and circuit applications, the impact on ESD protection strategies is studied. Classical protection approaches are critically examined regarding the latest technology developments and new requirements for IO interface circuits. A switch from bulk to FinFET technology is still regarded as a major disruption for product architecture and thus ESD.

Verification of CDM circuit simulation using an ESD evaluation circuit

In this work, the capability of circuit simulation to predict CDM robustness of integrated circuits and to determine weak circuit elements is studied. The applicability is demonstrated for an ESD evaluation circuit designed to enable the analysis and optimization of ESD protection strategies in an early design phase during the introduction of a new technology. CDM circuit simulation is compared to the measurement results of variations of this circuit in two different package types. Failure locations are verified with physical failure analysis. The failure locations and CDM failure levels were reproduced accurately with circuit simulation for all circuit and package variations.

Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 μm CMOS process

ESD protection for radio frequency (RF) applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfill these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 μm CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme. The optimization of the diodes is then a key point which is detailed. A trade-off has to be found between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as shallow trench isolation (STI) bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice.

Distributed ESD protection for high-speed integrated circuits

Conventional ESD guidelines dictate a large protection device close to the pad. The resulting capacitive load causes a severe impedance mismatch and bandwidth degradation. A distributed ESD protection scheme is proposed to enable a low-loss impedance-matched transition from the package to the chip. A simple resistive model adequately predicts the ESD behavior under stress according to the charged device and human body models. The large area of the distributed ESD scheme could limit its application to designs such as distributed amplifiers, rf transceivers, A/D converters, and serial links with only a few dedicated high-speed interfaces. The distributed ESD protection is compatible with high-speed layout guidelines, requiring only low-loss transmission lines in addition to a conventional ESD device.

Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain

The presented compact model for NMOS transistors combines both the high-current bipolar mode and the MOS mode considering modulation of the current gain β and gate coupling effects. For the studied 0.35 μm-CMOS devices, measurement and simulation correlate very well with respect to layout variations, fulfilling a prerequisite for the simulation guided synthesis and optimization of ESD protection structures and schemes. The open model interface also allows the use of existing proprietary MOS-models.

ESD evaluation methods for a charged device model

Through the investigation of several evaluation methods for charged device model (CDM) ESD, the following results have been found: (1) although the waveforms of the small capacitance method (SCM-10 pF, 0 /spl Omega/) and three commercial pieces of CDM equipment are different, the destructive voltage for dielectric failure are equivalent. SCM is an efficient and easy test method for high-speed ESD evaluation; (2) it is necessary to apply a different ESD protection strategy and circuit for CDM and SCM than for the human body model (HEM); (3) the destructive voltage for memory devices on the market ranges from 350 V to 4000 V.

Bi-modal triggering for LVSCR ESD protection devices

Abstract This paper addresses three aspects of LVSCR protection devices namely, LVSCR layout optimization, triggering techniques, and the impact of stress signal slew-rate on ESD performance. Circuit techniques to achieve bi-modal triggering for LVSCR ESD protection schemes are presented. The low voltage trigger mode operates when the chip is in packaging and assembly while the high voltage mode operates when the chip is in the final product board with the power supplies applied. The triggering techniques discussed here are particularly useful in conjuction with high speed I/Os and interface ICs. The paper also reports the impact of stress slew rates on the failure thresholds. In particular, it is shown that when the slew rate is increased from 0.2 to 0.4 A/ns, the SCR failure threshold decreases from that given by a second breakdown failure mode to the one dictated by an early oxide failure. The paper concludes with an analysis of the LVSCR layout parameters on its trigger and ESD clamping effectiveness.

ESD protection in a 3.3 V sub-micron silicided CMOS technology

An ESD protection strategy has been developed for a 3.3 V, silicided sub-micron CMOS process with MDD junctions which achieves ESD robustness to 3000 V on first silicon IC's. A silicide/MDD blocking process is used to produce effective and robust nMOST clamps that are the work horses for this protection strategy. Results show that protection for advanced technologies can be achieved if it is designed as part of the process.

A successful HBM ESD protection circuit for micron and sub-micron level CMOS

A successful ESD protection circuit depends on a clear understanding of the process parameters and design rules of a given fabrication process. This work will show an ESD protection scheme that protects CMOS well as minimum feature sizes ranging from micron to sub-micron scales. The primary protection device utilizes an SCR structure available from a N-Well CMOS process in conjunction with a series N-Well resistor. ESD immunity of > 2kV has been demonstrated on state of the art ASIC arrays using these structures.

Design for Electrostatic-Discharge (ESD) Protection in Telecommunications Products

Electrostatic discharge (ESD) can seriously damage electronic devices and affect the operation of the systems that contain them. Today, design for ESD protection has become a critical — and more difficult — consideration because of shrinking device feature sizes, high system operating speeds, factory automation, and the growth of uncontrolled user environments. To meet this challenge, designers must consider ESD protection early in the product-development process. The designer must also work with the factory engineer to identify performance and manufacturing process tradeoffs and assess their relative importance. Also, testing to customer requirements should be done early and often during the development process. This paper describes ways to limit the damaging effects of ESD at the device, circuit-pack, and system levels. As an example of device-level ESD-protection schemes, we present an approach employed at AT&T Microelectronics. We also review product testing for ESD, industry test standards, and future trends.