Error Detection And Correction Research Articles

Solar Energetic Particle Events Detected in the Housekeeping Data of the European Space Agency's Spacecraft Flotilla in the Solar System

AbstractDespite the growing importance of planetary Space Weather forecasting and radiation protection for science and robotic exploration and the need for accurate Space Weather monitoring and predictions, only a limited number of spacecraft have dedicated instrumentation for this purpose. However, every spacecraft (planetary or astronomical) has hundreds of housekeeping sensors distributed across the spacecraft, some of which can be useful to detect radiation hazards produced by solar particle events. In particular, energetic particles that impact detectors and subsystems on a spacecraft can be identified by certain housekeeping sensors, such as the Error Detection and Correction (EDAC) memory counters, and their effects can be assessed. These counters typically have a sudden large increase in a short time in their error counts that generally match the arrival of energetic particles to the spacecraft. We investigate these engineering datasets for scientific purposes and perform a feasibility study of solar energetic particle event detections using EDAC counters from seven European Space Agency Solar System missions: Venus Express, Mars Express, ExoMars‐Trace Gas Orbiter, Rosetta, BepiColombo, Solar Orbiter, and Gaia. Six cases studies, in which the same event was observed by different missions at different locations in the inner Solar System are analyzed. The results of this study show how engineering sensors, for example, EDAC counters, can be used to infer information about the solar particle environment at each spacecraft location. Therefore, we demonstrate the potential of the various EDAC to provide a network of solar particle detections at locations where no scientific observations of this kind are available.

Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss

Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess timing margin but suffer from miss detection risk due to inactivation of the critical paths. We propose a negative margin timing error detection (NMED) method to increase detection reliability, which further pushes the timing margin to beyond eliminating it, by monitoring less critical yet often activated paths instead of the most critical but rarely activated paths. To further reduce its area overhead, we propose a low-overhead low-latency transition detector (TD) with only 16 transistors and a transmission gate-based short-path (SP) padding method to extend SPs efficiently. We implement all the proposed techniques on a neural network (NN) accelerator using the 28-nm CMOS process. Chip measurement results show that our NMED method achieves up to 238% frequency gain or 59% power reduction at near-threshold voltage (NTV) while solving the miss detection risk and conquering the accuracy loss problem in error detection of NN accelerators.

A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead

In-situ timing error detection and correction (EDAC) structure is widely adopted in timing-error resilient circuits to reduce the conservative timing guardband induced by process, voltage, and temperature (PVT) variations. However, it introduces the latch-based datapath as well as extra detection and propagation logic, therefore challenges the design-for-testability (DFT) implementation. In this article, we propose a novel DFT-compatible EDAC structure with significant signal control simplification and test-pattern complexity reduction, featuring low area and test overhead. This structure leverages a new scannable EDAC cell (SEDC) which can be configured for timing EDAC in normal mode, or for shift operations as a flip-flop in scan mode. Specifically, the proposed detection logic can be controlled succinctly in scan shift operations and then observed via the global error propagation logic with simple control signal configurations during the test. Therefore, the sophisticated test pattern generation and critical path sensitization are removed. Based on the structure, a shift-based test method is presented to cover the EDAC structure with a low test pattern complexity and test time overheads. As compared with previous works, the proposed SEDC saves 30.5% area, 16.6% power, and 20.3% delay. Besides, our test method cooperating with the proposed EDAC structure reduces <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$149\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$23\times $ </tex-math></inline-formula> static and at-speed test patterns, respectively, together with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$232\times $ </tex-math></inline-formula> static test cycles, and up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25\times $ </tex-math></inline-formula> at-speed test cycles on average, which proves the effectiveness for DFT.

A Unified Clock-Gated Error Correction Scheme with Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router

Network-on-chip (NoC) has played a vital role in enabling high-speed and energy-efficient data communication among different cores in a multi-or many-core System-on-Chip (SoC). To mitigate the pessimistic timing margin reversed for severe process, voltage, and temperature (PVT) variations, we presented a wide supply voltage range router with a novel error detection and correction (EDAC) technique adopted in its latch-based pipeline for high energy efficiency. Especially, a unified clock-gated error correction scheme is presented to address dynamic timing errors under PVT variations and functional pipeline stalls when occurring allocation failure (packet fails to obtain an output port) or flow control (the next router stalls the current packet transmitting) in one cycle. Moreover, a latch-based pipeline structure with three non-overlapped clocks is adopted to further reduce the short-path padding overhead, which is significantly increased in the ultra-low voltage (ULV) regime. Consequently, we prototyped a 2 × 2 2D mesh NoC test chip with 28-nm CMOS technology. Compared with the margined baseline with a 10% VDD drop, measurement results show that the proposed router enables 1.4×, 32.4%, and 7.5% improvements in frequency, energy, and area, respectively. Furthermore, the proposed techniques can reduce packet loss by 200× and increase throughput by 19.9% for the NoC at 0.4 V, 25∘C.

Influences of well contact on multiple-cell upsets in 28 nm SRAM

In order to study the effects of the feature size reduction and well contact placement on the characterization of topology patterns and the charge collection mechanism of device heavy ion single event multiple upset on a nanometer scale, the heavy ion single event effect experiment on the domestic 28 nm static random-access memory (SRAM) is carried out on the experimental platform of HI-13 heavy ion accelerator in Beijing. Based on the mapping relationship between the logical address and physical address of the device, the experimental data are processed, and the 28 nm SRAM heavy ion single event upset cross section curves, multiple upset percentage, and multiple upset topology patterns are obtained. The results are compared with those of heavy ion single event effect experiments in 65 nm SRAM, showing that under the influences of factors such as feature size reduction and lower operating voltage, the heavy ion single event upset threshold and the bit upset saturation cross section of 28 nm SRAM decrease significantly. In the direction perpendicular to the well, owing to the reduced 28 nm SRAM feature size, even if the single nucleon energy of the incident high LET (linear energy transfer) heavy ion is low, its deposited charge is sufficient to affect the three SRAM cells across the well direction due to the combined effect of ion track coverage, well potential modulation caused by the parasitic bipolar amplification effect and carrier diffusion, resulting in the fact that the 28 nm SRAM topology pattern has a shape of &lt;i&gt;n&lt;/i&gt; rows × 3 columns, which poses new challenges and requirements for the anti-radiation hardened technology with scrubbing and EDAC (error detection and correction). Owing to the global well contact deployment, the charge deposited by the incident ions in the well far away from the well contact is difficult to discharge quickly, and the parasitic bipolar amplification effect lasts longer. The charge sharing competition between two p-channel metal oxide semiconductor in SRAM cell causes the single event upset recovery, which is the fundamental reason why the discontinuity of multiple upset topology pattern appears in 28 nm SRAM. This study provides a new anti-radiation hardened idea for suppressing the single event upset by using the parasitic bipolar amplification in the future.

Error Detection and Correction Method Toward Fully Memristive Stateful Logic Design

Implementing stateful logic based on memristors is a promising approach for the development of a highly efficient in‐memory computing paradigm, wherein the data transmission between the controller and memory is largely alleviated. However, the deviation of the electrical behavior of memristors causes errors in the execution process of the stateful logic. Consequently, a reliability issue arises that must be carefully addressed. Here, a method of error detection and correction (EDC) based on memristor‐based stateful logic operation is proposed for the IMP stateful logic gate (PMR‐two‐2IMP). Leveraging the concept of redundancy, error detection is achieved with the assistance of a stateful NOR logic gate, while a composite stateful OR logic gate is used for error correction. In the simulated validation, the concept of redundancy is employed to improve the accuracy of EDC. Finally, the feasibility of the proposed method for practical devices (TiN/TaO x /HfO x /TiN) is demonstrated using a circuit platform equipped with a 1T1R crossbar array.

Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

This article presents a timing error detection and correction (EDaC) technique optimized for near-/sub-threshold operation to recover energy lost in the conventional signoff margins. The presented EDaC requires no modifications to the processor pipeline and avoids imposing additional hold constraints on monitored paths by instantaneously checking for late activity. Furthermore, two correction methods are discussed: a simple clock gating method and a low cycle overhead clock stretching method. Both provide robust last-minute error prevention. The EDaC is applied in a near-/sub-threshold implementation of the CoolFlux DSP processor and infers only a 2.8% and 2.1% area overhead for the detection and correction, respectively. Silicon measurements validate the EDaC system from 0.25 to 0.7 V (1–200 MHz) and show that it recovers all voltage margins in the near-/sub-threshold region. The design achieves a minimum energy point (MEP) of 8.1 pJ/cycle at 0.34 V and 10 MHz. Here, the EDaC technique reduces the energy consumption by 48%–17.6% with respect to the signoff margins depending on their conservatism, and it enables the processor to operate with only 12% energy overhead compared to its ideal non-margined critical operation point.

Galactic cosmic ray modulation at Mars and beyond measured with EDACs on Mars Express and Rosetta

Galactic cosmic rays (GCRs) are an intrinsic part of the heliospheric radiation environment and an inevitable challenge to long-term space exploration. Here we show solar-cycle-induced GCR modulation at Mars in the period 2005–2020, along with GCR radial gradients, by comparing Mars Express and Rosetta engineering parameters to sunspot number time series. The engineering parameters used are the error detection and correction (EDAC) counters, cumulative counters that are triggered by charged energetic particles that cause memory errors in onboard computers. EDAC data provide a new way of gaining insight into the field of particle transport in the heliosphere; these data also allow us to complement dedicated radiation instrumentation as EDAC software is present on all spacecraft. This dataset was used to capture variations in GCRs in both space and time, yielding the same qualitative information as ground-based neutron monitors. Our analysis of the Mars Express EDAC parameter reveals a strong solar cycle GCR modulation, with a time lag of ∼5.5 months. By combining Mars Express with Rosetta data, we calculate a 4.7 ± 0.8% increase in EDAC count rates per astronomical unit, which we attribute to a radial gradient in GCR fluxes in accordance with established literature. The potential of engineering data for scientific purposes remains mostly unexplored. The results obtained from this work demonstrate, for the first time for heliophysics purposes, the usefulness of the EDAC engineering parameter, the usefulness of data mining, and the utility of keeping missions operational for many years, all of which provide complimentary data to nominal science instruments.

Research on EDAC Schemes for Memory in Space Applications

Memory used for storing the configuration bitstream of field programmable gate array in space applications often encounters single event upset problems, which may disrupt the integrity of data in memory and lead to unpredictable failures. For commercial memories used in low Earth orbit (LEO), single-bit errors and double-byte errors account for a large proportion. Meanwhile, error detection and correction (EDAC) schemes, e.g., triple modular redundancy, linear block codes, memory scrubbing, and the combination of these schemes, are very popular in LEO missions. To further these works, a novel EDAC scheme with cascaded “Bose–Chaudhuri–Hocquenghem and cyclic redundancy check” codes and a proper scrubbing method is presented in this paper. The performance of the proposed design is measured and compared with state-of-the-art EDAC schemes in terms of hardware overhead, time overhead and error correction and detection capabilities. It is concluded that the proposed EDAC scheme is better suited for memory in space applications.

Latency optimized clustered error mitigation for multi-level flash memory using product code

Soft errors due to radiation-induced multi-bit upsets (MBUs) are very prominent in the present flash memories built with ultra large scale VLSI technology. Use of multi-level cells in flash memories increase the chance of adjacent MBUs or clustered error. Single bit error detection and correction (EDAC) codes are not enough to mitigate the effect of clustered error due to their small error correction capability. On the other hand, commonly used multi-bit EDAC codes have large overhead, complex decoding circuitry, high error correction latency and are unable to correct large number adjacent erroneous bits. In this paper, we have proposed a product code coined as linear shortened block code based product code (LSBCPC) for mitigation of clustered error in the flash memory devices. LSBCPC utilizes latency optimized scalable shortened block code as the component code and can correct higher number of adjacent erroneous bits in memory devices compared to the other state of the art solutions. The proposed LSBCPC promises better error correction coverage with 28%, 14%, and 13% reduction in terms of redundant bits, 13%, 11%, and 10% reduction in terms of area and 24%, 26%,and 22% reduction in terms of latency in 16 × 16, 32 × 32 and 64 × 64 memory devices respectively compared to the highly cited research work. The performance of the proposed method is validated in terms of redundant bits, error correction coverage, mean error to failure, area consumption, power utilization and decoding latency.

Model matching inclusion for input/state asynchronous sequential machines with constraint on the length of control input sequences

In this paper, the model matching inclusion problem for input/state asynchronous sequential machines (ASMs) is studied in the framework of corrective control. The considered ASM receives the external input with various frequencies which hinder full use of inherent reachability of the machine. We elucidate the existence condition and design procedure for a state feedback corrective controller that makes the closed-loop system have the largest behavior contained by a given reference model. To demonstrate the practicality of the proposed control scheme, experimental studies on an asynchronous error detection and correction (EDAC) module are conducted by implementing the controller and machine on the field-programmable gate array (FPGA) system.

Mitigating single event upset of FPGA for the onboard bus control of satellite

This paper proposes a hybrid anti-radiation method to enhance the reliability of Field Programmable Gate Array (FPGA), which is being applied more and more in the commercial satellite. The method utilizes the advantages of Error Detection And Correction (EDAC) and Triple Modular Redundancy (TMR). Different bus control units are improved by different anti-radiation techniques. For finite state machine, dual-port Block Random Access Memory and EDAC are utilized. EDAC is also used to enhance First In First Output unit. For the simple control register, TMR is applied to improve its anti-radiation. This hybrid method can avoid the accumulated error of TMR and reduce the complexity of system. Experimental results show that the proposed method can correct 1-bit error and detect 2-bit error effectively.

A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS

Excessive timing margins are usually added in the wide-voltage-range design due to process, voltage and temperature (PVT) variations, which can be eliminated by adaptive voltage scaling (AVS). Some traditional Razor-based designs replace endpoint flip-flops with latches and ensure data sampled correctly. The duration of time-borrowing and the short path problem make the minimum-delay constraint worthy of consideration. To overcome the minimum-delay problem in the latch-based error detection and correction (EDAC) techniques, we propose a solution using a pulsed-latch and transition detector (TD). This method utilizes time-borrowing characteristics of the latch to ensure the correct function. To detect timing violations and minimize area overhead, we design a 15-transistor transition detector which is able to operate at a wide voltage range, from near-threshold voltage (NTV) to super-threshold voltage (STV). To minimize the overhead of pulse generators, a physical allocation-aware pulse generator insertion algorithm is presented to identify each desired group of a pulse generator and a pulsed-latch group. The proposed scheme is implemented in an 8-bit AES circuit through an automatic insertion flow and fabricated in a 28nm CMOS process. Chip measurements demonstrate that the whole design achieves up to 64.3% energy saving as compared to the conventional worst-case design at a small price of 4.3% area overhead.

How Much Do Solar Cycle Variations Impact Long-Term Effect Predictions at LEO?

An eight-year long flight database from an error detection and correction (EDAC) counter implemented onboard an altimeter flying on CryoSat-2 spacecraft at 715-km altitude is analyzed to investigate the impact of solar cycle variations on long-term effect predictions. In situ observations are then compared to various specification models including legacy models as well as models under developments.

Power Efficient and High-Accuracy Approximate Multiplier with Error Correction

Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.

Characterization of Single Event Cell Upsets in a Radiation Hardened SRAM in a 40 nm Bulk CMOS Technology

A large amount of data needs to be stored in integrated circuits when data are being processed. The integrated circuits contain a large amount of static random access memory (SRAM) due to its high level of integration and speed. SRAM units should be as small as possible to achieve higher storage density. In this work, the features of single cell upsets (SCUs) and multiple cell upsets (MCUs) in a full custom SRAM are tested for a 40 nm bulk CMOS technology node, and Ge (linear energy transfer (LET) = 37.3 MeV cm2/mg), Cl (LET = 13.1 MeV cm2/mg), Al (LET = 8.6 MeV cm2/mg), O (LET = 3.1 MeV cm2/mg), and Li (LET = 0.5 MeV cm2/mg) particles are used. The test results show that the total single cell upset events are 2,000,147, 1,124,269, 413,100, 311,311, and 47,815 under the irradiation of Ge, Cl, Al, O, and Li, respectively. Moreover, due to single event upset reversal mechanism, multiple cell upsets significantly decrease. The total multiple cell upset events are 10, 4, 0, 0, and 0 under the irradiation of Ge, Cl, Al, O, and Li, respectively. There are a lot of single cell upsets appearing under Ge, Cl, Al, O, and Li exposure. The number is increasing with increasing LET, which means that well contacts still need optimization in the full custom SRAM. Close spacing of well contacts or increasing contacts are the approaches used to drain the excess carriers quickly, and error detection and correction (EDAC) is used for SRAM technology. The features show that SCUs have become a major source of soft errors for the full custom SRAM. Combining close spacing of well contacts with error detection and correction (EDAC) and a well engineering scheme are used to reduce single cell upsets, although there are a few MCUs which are inevitable. Radiation hardened by design schemes needs to be further improved.

Completion Detection-Based Timing Error Detection and Correction in a Near-Threshold RISC-V Microprocessor in FDSOI 28 nm

This letter presents a novel timing error detection and correction (EDaC) technique to reduce design margins in a near/sub-threshold RISCV-IM32 microprocessor. The proposed technique takes a snapshot of the datapath’s activity just before the launch of the next clock to determine if a timing error will occur. If so, it prevents the error at the last moment by gating the clock with one cycle. This avoids imposing additional hold constraints on the design and removes the need for a complex correction mechanism. The design is implemented in FDSOI 28 nm and achieves a margined minimum energy point (MEP) of 1.32 pJ/cycle at 3 MHz and 0.434 V. The EDaC technique robustly eliminates all voltage margin, resulting in an improved MEP of 0.92 pJ/cycle and 0.345 V at the same frequency.

A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS

This article presents a variation-resilient microprocessor architecture with a two-level timing error detection and correction (EDAC) system. The proposed EDAC system first performs circuit-level error correction through time borrowing when a timing error occurs and subsequently employs a system-level error correction scheme if the timing error is relatively large and cannot be resolved within a cycle. Therefore, compared with the existing EDAC approaches, a processor using the proposed EDAC system can achieve better performance and energy efficiency under different operating conditions without incurring significant implementation effort and overhead. The proposed EDAC system was designed and implemented on an ARM Cortex-M0 microprocessor using a 28-nm CMOS process. The measurement results show that the proposed processor achieves 60.5% reduction in energy by operating under a 0.36-V lower supply voltage and at the same frequency as the baseline processor. In addition, it achieves a 37.1% reduction in minimum energy consumption compared to the baseline design.

TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS

Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess timing margin but suffer from the short-path (SP) issue where SPs must be padded to exceed the detection window. SP padding (SPP) is similar to, but severer than, hold time fixing. Thus, it incurs significant area overhead, especially when working in the near-threshold region. In this article, we propose a transmission gate-based SPP (TG-SPP) method, which uses only one transmission gate to extend an SP to the negative clock phase while keeping the critical paths unaffected. Compared with the two-phase latch way or the conventional padding with tens to hundreds of buffers in an SP, our method efficiently decreases the overhead. We develop transmission gate insertion rules and an automatic insertion flow to overcome the complicated intersection problem of short and critical paths. To further reduce the EDAC area overhead, we also propose a lightweight error detection latch that has only two extra transistors compared to a conventional 24-T flip-flop for the conventional way. We implement all the proposed techniques in an SHA-256 chip using the 28-nm CMOS process. Results show that our TG-SPP method achieves the same padding effect as the two-phase latch-based method while reducing both the glitch power and sequential area overhead by a factor of 6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> . The fabricated resilient chips are measured to achieve 55%–405% frequency improvement and 38.6%–69.4% power saving compared with the typical margined baseline at the near-threshold region.

Fault‐tolerant method for anti‐SEU of embedded system based on dual‐core processor

The development of space applications based on commercial system on chip (SOC) FPGA devices has become an important direction for the development of aerospace technology, but single event upsets (SEUs) in space is a difficult problem for commercial SOC FPGAs for space applications. This article presents an anti-anti method for ARM processors in SOC FPGA. This method makes full use of the hardware resources of dual-core ARM in SoC FPGA and improves the system's anti-SEU capability through dual-core mutual-check and recovery mechanisms. At the same time, the data stream and control flow fault tolerant are used to improve the anti-SEU capability within the processor. Error detection and correction (EDAC) and triple modular redundancy (TMR) are used to improve anti-SEU capability of the data flow. A two-level watchdog and ARM exception handling are used to achieve the anti-SEU capability of the control flow. Experimental results show that the two-level fault-tolerance mechanism proposed here improves the system's anti-SEU capability without adding additional hardware resources. This method is currently carrying out satellite-borne ground application verification.