Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

Abstract

This article presents a timing error detection and correction (EDaC) technique optimized for near-/sub-threshold operation to recover energy lost in the conventional signoff margins. The presented EDaC requires no modifications to the processor pipeline and avoids imposing additional hold constraints on monitored paths by instantaneously checking for late activity. Furthermore, two correction methods are discussed: a simple clock gating method and a low cycle overhead clock stretching method. Both provide robust last-minute error prevention. The EDaC is applied in a near-/sub-threshold implementation of the CoolFlux DSP processor and infers only a 2.8% and 2.1% area overhead for the detection and correction, respectively. Silicon measurements validate the EDaC system from 0.25 to 0.7 V (1–200 MHz) and show that it recovers all voltage margins in the near-/sub-threshold region. The design achieves a minimum energy point (MEP) of 8.1 pJ/cycle at 0.34 V and 10 MHz. Here, the EDaC technique reduces the energy consumption by 48%–17.6% with respect to the signoff margins depending on their conservatism, and it enables the processor to operate with only 12% energy overhead compared to its ideal non-margined critical operation point.