Completion Detection-Based Timing Error Detection and Correction in a Near-Threshold RISC-V Microprocessor in FDSOI 28 nm

Abstract

This letter presents a novel timing error detection and correction (EDaC) technique to reduce design margins in a near/sub-threshold RISCV-IM32 microprocessor. The proposed technique takes a snapshot of the datapath’s activity just before the launch of the next clock to determine if a timing error will occur. If so, it prevents the error at the last moment by gating the clock with one cycle. This avoids imposing additional hold constraints on the design and removes the need for a complex correction mechanism. The design is implemented in FDSOI 28 nm and achieves a margined minimum energy point (MEP) of 1.32 pJ/cycle at 3 MHz and 0.434 V. The EDaC technique robustly eliminates all voltage margin, resulting in an improved MEP of 0.92 pJ/cycle and 0.345 V at the same frequency.