Abstract
Memory used for storing the configuration bitstream of field programmable gate array in space applications often encounters single event upset problems, which may disrupt the integrity of data in memory and lead to unpredictable failures. For commercial memories used in low Earth orbit (LEO), single-bit errors and double-byte errors account for a large proportion. Meanwhile, error detection and correction (EDAC) schemes, e.g., triple modular redundancy, linear block codes, memory scrubbing, and the combination of these schemes, are very popular in LEO missions. To further these works, a novel EDAC scheme with cascaded “Bose–Chaudhuri–Hocquenghem and cyclic redundancy check” codes and a proper scrubbing method is presented in this paper. The performance of the proposed design is measured and compared with state-of-the-art EDAC schemes in terms of hardware overhead, time overhead and error correction and detection capabilities. It is concluded that the proposed EDAC scheme is better suited for memory in space applications.
Highlights
It is well known that data stored in memory chips suffer from single event upsets (SEUs) in space applications
This paper focuses on hardware implemented error detection and correction (EDAC) schemes for memory in space applications
There are two kinds of scrubbing operation, one is scrubbing based on the universal asynchronous receiver/transmitter (UART) in a fixed interval, the other is scrubbing based on the EDAC circuit [23,24]
Summary
It is well known that data stored in memory chips suffer from single event upsets (SEUs) in space applications. For the transmission of secure data between devices and its local memory, triple modular redundancy (TMR) is widely used for anti-SEU design, but its probabilistic error correction ability can cause cumulative error [2,3]. Another disadvantage of TMR is its large memory overhead (200%) [4]. Linear block codes with excessive errorcorrecting capabilities (e.g., LDPC, Reed–Solomon Code) are not necessary because they will increase design complexity and cause large hardware overhead [7,8]. Some researchers have found a transistor-level EDAC method with small hardware overhead, which helps design the radiation-hardened memory cell library but is not suitable for error correction, in Table 1 [10,11,12]
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
