Error Detection and Correction Method Toward Fully Memristive Stateful Logic Design

Abstract

Implementing stateful logic based on memristors is a promising approach for the development of a highly efficient in‐memory computing paradigm, wherein the data transmission between the controller and memory is largely alleviated. However, the deviation of the electrical behavior of memristors causes errors in the execution process of the stateful logic. Consequently, a reliability issue arises that must be carefully addressed. Here, a method of error detection and correction (EDC) based on memristor‐based stateful logic operation is proposed for the IMP stateful logic gate (PMR‐two‐2IMP). Leveraging the concept of redundancy, error detection is achieved with the assistance of a stateful NOR logic gate, while a composite stateful OR logic gate is used for error correction. In the simulated validation, the concept of redundancy is employed to improve the accuracy of EDC. Finally, the feasibility of the proposed method for practical devices (TiN/TaO x /HfO x /TiN) is demonstrated using a circuit platform equipped with a 1T1R crossbar array.