Electrothermal Annealing Research Articles

BEOL Compatible Ultra-Thin ITO Transistor With Performance Recoverable Capability by in Situ Electrothermal Annealing

BEOL Compatible Ultra-Thin ITO Transistor With Performance Recoverable Capability by in Situ Electrothermal Annealing

3D Neuromorphic Hardware with Single Thin-Film Transistor Synapses Over Single Thin-Body Transistor Neurons by Monolithic Vertical Integration.

Neuromorphic hardware with a spiking neural network (SNN) can significantly enhance the energy efficiency for artificial intelligence (AI) functions owing to its event-driven and spatiotemporally sparse operations. However, an artificial neuron and synapse based on complex complementary metal-oxide-semiconductor (CMOS) circuits limit the scalability and energy efficiency of neuromorphic hardware. In this work, a neuromorphic module is demonstrated composed of synapses over neurons realized by monolithic vertical integration. The synapse at top is a single thin-film transistor (1TFT-synapse) made of poly-crystalline silicon film and the neuron at bottom is another single transistor (1T-neuron) made of single-crystalline silicon. Excimer laser annealing (ELA) is applied to activate dopants for the 1TFT-synapse at the top and rapid thermal annealing (RTA) is applied to do so for the 1T-neuron at the bottom. Internal electro-thermal annealing (ETA) via the generation of Joule heat is also used to enhance the endurance of the 1TFT-synapse without transferring heat to the 1T-neuron at the bottom. As neuromorphic vision sensing, classification of American Sign Language (ASL) is conducted with the fabricated neuromorphic module. Its classification accuracy on ASL is ≈92.3% even after 204800 update pulses.

Investigation of Mechanical Stability during Electro-thermal Annealing in a 3D NAND Flash Memory String

Simulation studies are performed for better mechanical stability during using electro-thermal annealing (ETA) in 3D NAND flash memory. It is revealed that the mechanical stress is closely associated with the cell temperature and thermal expansion characteristic. Based on the thermal and material knowledges, various approaches for reducing the mechanical stress are proposed in terms of modification of bias configuration, alternative materials, and novel structure.

Sub-Second Joule-Heated RuO2-Decorated Nitrogen- and Sulfur-Doped Graphene Fibers for Flexible Fiber-type Supercapacitors.

Graphene-based fiber-shaped supercapacitors (FSSCs) have received considerable attention as potential wearable energy storage devices owing to their simple operating mechanism, flexibility, and long-term stability. To date, energy storage capacities of supercapacitors have been significantly improved via strategies such as heteroatom doping and the incorporation of pseudocapacitive metal oxides. Herein, we develop a novel and scalable direct-hybridization method that combines heteroatom doping and metal oxide hybridization for the fabrication of high-performance FSSCs. Using porous and highly conductive nitrogen and sulfur co-doped graphene fibers (NS-GFs) as self-heating units, we successfully convert ruthenium hydroxide anchored to the surface into ruthenium oxide nanoparticles after programmed sub-second electrothermal annealing without structural damage of the fibers. The resulting fibers show an increased gravimetric capacitance of 68.88 F g-1 compared to that of the pristine NS-GF (8.32 F g-1), excellent cyclic stability maintaining 96.67% of the initial capacitance after 20 000 continuous charging/discharging cycles, and good mechanical flexibility. The findings of this work advocate a successful Joule heating strategy for preparing high-performance graphene-based metal oxide hybrid FSSCs for use in energy storage applications.

Vacuum Inner Spacer to Improve Annealing Effect during Electro-Thermal Annealing of Nanosheet FETs.

Electro-thermal annealing (ETA) in a MOSFET utilizes Joule heating. The high-temperature heat effectively cures gate dielectric damages induced by electrical stresses or ionizing radiation. However, even though ETA can be used to improve the reliability of logic and memory devices, applying ETA in state-of-the-art field-effect transistors (FETs) such as nanosheet FETs (NS FETs) has not yet been demonstrated. This paper addresses the heat distribution characteristic of an NS FET considering the application of ETA, using 3D simulations. A vacuum inner spacer is newly proposed to improve annealing effects during ETA. In addition, evaluations of the device scaling and annealing effect were performed with respect to gate length, nanosheet-to-nanosheet vertical space, and inner spacer thickness. Guidelines for ETA in NS FETs can be provided on the basis of the results.

Characteristics of noise degradation and recovery in gamma-irradiated SOI nMOSFET with in-situ thermal annealing

This paper demonstrates a procedure for complete in-situ recovery of on-membrane CMOS devices from total ionizing dose (TID) defects induced by gamma radiation. Several annealing steps were applied using an integrated micro-heater with a maximum temperature of 365 °C. The electrical characteristics of the on-membrane nMOSFET are recorded prior and during irradiation (up to 348 krad (Si)), as well as after each step of the in-situ thermal annealing. High-resolution current sampling measurements reveal the presence of oxide defects after irradiation, with a clear dominant single-trap signature in the random telegraph noise (RTN) traces. Drain current over time measurements are used for the trap identification and further for the defects' parameters extraction. The power spectral density (PSD) curves confirm a clear dominance of the RTN behavior in the low-frequency noise. A radiation-induced oxide trap is detected at 5.4 nm from the Si-SiO2 interface, with an energy of 0.086 eV from the Fermi level in the bandgap. After annealing, the RTN behavior vanishes with a further important reduction of flicker noise. Low-frequency noise measurements of the transistor confirmed the neutralization of oxide defects after annealing. The electro-thermal annealing of the nMOSFET allows a total recovery of its original characteristics after being severely degraded by radiation-induced defects.

Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs.

Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In order to maximize power efficiency during electro-thermal annealing (ETA), applying gate module engineering was more suitable than engineering the isolation or source drain modules.

Impact of Dielectrics in SOI FinFET for Lower Power Consumption in Punch-through Current-based Local Thermal Annealing

Impact of device geometric structures and materials is discussed to improve power efficiency of punch-through current based electro-thermal annealing (ETA). Various sensitivities that affect device temperature during ETA are extracted and compared. Then, dielectric engineering in terms of thermal conductivity and thermal isolation is suggested for better power management. Finally, time-dependent characteristics with various thicknesses of buried dielectric layer are discussed to improve annealing speed. As a result, the contents of this paper provide a guide to better application of ETA.

Highly electroconductive lightweight graphene fibers with high current-carrying capacity fabricated via sequential continuous electrothermal annealing

The recent increase in demand for miniaturized electronics has necessitated the development of lightweight, narrow, and flexible channels with high current density as next-generation conductors. Despite the high electrical conductivity and current-carrying capacity (i.e., ampacity) of conventional metal conductors (e.g., copper and gold), their high mass density should be overcome for potential weight-critical applications. In this regard, defect-free graphene fibers (GFs) are excellent alternatives owing to their lightweight and high electroconductivity. In this study, GFs were electrothermally annealed at ~3000 K for a very short time (~50 s) via sequential continuous current injection. This treatment led to the carbonization and subsequent graphitization of the GFs, resulting in successful reparation of the structural disorder and crystalline defects of the GFs. This continuous process is advantageous for scaled production of highly electroconductive GFs. The resultant meter-scale GFs exhibit an electrical conductivity of 2721 S cm−1, maximum ampacity of 3.84 × 104 A cm−2, and specific current-carrying capacity of 4.67 × 104 A cm g−1, which are higher than the corresponding values of a commercial copper wire. This study provides a versatile and cost-effective technique for the development of advanced fibers and films as lightweight conductors for relevant applications.

Triboelectric nanogenerator for a repairable transistor with self-powered electro-thermal annealing

A metal-oxide-semiconductor field-effect transistor (MOSFET), which is an elementary unit of microelectronics, was repaired by self-powered electro-thermal annealing with the aid of a wind-driven triboelectric nanogenerator (TENG). It was thermally cured by Joule heat that originated electrically from the MOSFET itself. The configuration of the self-curable system is composed of a MOSFET with an embedded built-in Joule heater and a wind-driven TENG. This self-curable feature is attractive for the construction of remote wireless sensor networks, is capable of sustainable operation for long-term use, has high immunity against external environmental stress as well as internal operation stress, and can reduce labor during the periodic replacement of power sources. • Self-powered electro-thermal annealing was performed to cure the damaged electronic devices. • Electrical output of triboelectric nanogenerator was firstly used as Joule heat generation. • The electronic device was successfully cured by the SP-ETA from plural damage factors: γ-ray and hot carrier injection. • The Self-powered electro-thermal annealing was also verified at charge-trap based flash memory devices.

Power reduction for recovery of a FinFET by electrothermal annealing

A strategy of reducing the power consumption to cure gate dielectric damage by electrothermal annealing (ETA) is proposed. A tri-gate FinFET was fabricated to demonstrate the damage curing by the ETA. Localized Joule heat induced by high current flowing through dual gate electrodes successfully annealed the damaged gate dielectric. Furthermore, a design methodology to save power consumption during the ETA was explored. Electrical measurements and simulations were performed considering scaling-down and material engineering points of view. This work contributes to improving the reliability of the FinFET by developing the ETA approach with reduced power consumption.

Features of the Postgrowth Thermal and Electrothermal Treatment of Nominally Pure and Heavily Doped Lithium–Niobate Crystals

It is established that the postgrowth thermal and electrothermal annealing of heavily doped LiNbO3:ZnО and LiNbO3:MgО crystals differ greatly from such processes for nominally pure LiNbO3 crystals of congruent composition. Ways of optimizing the technological regimes of monodomenization for heavily doped lithium–niobate crystals are shown.

Reversible and Precisely Controllable p/n-Type Doping of MoTe2 Transistors through Electrothermal Doping.

Precisely controllable and reversible p/n-type electronic doping of molybdenum ditelluride (MoTe2 ) transistors is achieved by electrothermal doping (E-doping) processes. E-doping includes electrothermal annealing induced by an electric field in a vacuum chamber, which results in electron (n-type) doping and exposure to air, which induces hole (p-type) doping. The doping arises from the interaction between oxygen molecules or water vapor and defects of tellurium at the MoTe2 surface, and allows the accurate manipulation of p/n-type electrical doping of MoTe2 transistors. Because no dopant or special gas is used in the E-doping processes of MoTe2 , E-doping is a simple and efficient method. Moreover, through exact manipulation of p/n-type doping of MoTe2 transistors, quasi-complementary metal oxide semiconductor adaptive logic circuits, such as an inverter, not or gate, and not and gate, are successfully fabricated. The simple method, E-doping, adopted in obtaining p/n-type doping of MoTe2 transistors undoubtedly has provided an approach to create the electronic devices with desired performance.

Highly Biased Linear Condition Method for Separately Extracting Source and Drain Resistance in MOSFETs

A highly biased linear current method (HBLCM) for separately extracting source and drain resistance ( ${R}_{S}$ and ${R}_{D}$ ) in MOSFETs is proposed. The technique can be applied to a single device by using simple modeling. Compared to other methods, it provides accurate values of ${R}_{S}$ and ${R}_{D}$ because it considers carrier mobility degradation. The method basically uses linear current versus gate voltage ( ${I}_{\text {DS}} - {V}_{\text {GS}}$ and ${I}_{\text {SD}} - {V}_{\text {GD}}$ ) characteristics before and after the source/drain interchange ( ${I}_{\text {DS}}$ and ${I}_{\text {SD}}$ ). Afterward, by using the traditional Y-function and subsequent resistance modeling in a highly biased linear condition, ${R}_{S}$ and ${R}_{D}$ can be separately extracted. In order to evaluate and verify the accuracy of HBLCM, an external resistor was intentionally connected to a source electrode of a device, and the resulting change in source resistance was detected using the proposed method. Moreover, to demonstrate an application of the proposed method, internal resistance deliberately created by hot-carrier injection (HCI) was linked to a drain electrode, thereby changing drain resistance. The changed drain resistance was also sensed by the HBLCM. Afterward, the HCI-stressed device was cured by electrothermal annealing driven by Joule heating, and the recovery was again clearly observed using the proposed method.

Localized Electrothermal Annealing with Nanowatt Power for a Silicon Nanowire Field-Effect Transistor.

This work investigates localized electrothermal annealing (ETA) with extremely low power consumption. The proposed method utilizes, for the first time, tunneling-current-induced Joule heat in a p-i-n diode, consisting of p-type, intrinsic, and n-type semiconductors. The consumed power used for dopant control is the lowest value ever reported. A metal-oxide-semiconductor field-effect transistor (MOSFET) composed of a p-i-n silicon nanowire, which is a substructure of a tunneling FET (TFET), was fabricated and utilized as a test platform to examine the annealing behaviors. A more than 2-fold increase in the on-state (ION) current was achieved using the ETA. Simulations are conducted to investigate the location of the hot spot and how its change in heat profile activates the dopants.

Electrothermal Annealing to Enhance the Electrical Performance of an Exfoliated MoS2 Field-Effect Transistor

An electrothermal annealing (ETA) was applied to improve the ON-state current ( ${I} _{ \mathrm{\scriptscriptstyle ON}}$ ) of an exfoliated MoS2 field-effect transistor (FET). The ETA uses localized Joule heat generated by current flowing through the source and drain of the device. Process-induced contaminants in both the MoS2 channel and MoS2-metal junctions were reduced. Electrical characterization, including the extraction of mobility and parasitic resistance, was performed to analyze the annealing effects. Numerical thermal simulations were also performed to provide insight on parameters to optimize the ETA process since the MoS2 flakes have diverse sizes and asymmetric shapes in the exfoliation-based MoS2 FETs.

LF Noise Analysis for Trap Recovery in Gate Oxides Using Built-In Joule Heater

The importance of the reliability of gate oxide materials is increasing continuously as CMOS technology advancing. Joule heating to induce localized high temperature via a built-in gate heater has recently been introduced as a rapid and efficient method to cure instances of gate oxide damage, including damaged interface traps and bulk traps in the gate oxide. In this paper, spatially distributed deep oxide traps were generated by Fowler–Nordheim (FN) stress, and a recovery process by electrothermal annealing (ETA) using local Joule heat was clearly demonstrated with low-frequency (LF) noise characteristics. The generation and recovery of the oxide traps were quantitatively analyzed with LF noise, and the results showed that the border traps generated by the FN stress were cured by ETA. The recovery process was predominantly affected by the applied gate voltage and the duration. Excessive gate voltage beyond the critical value permanently destroyed the gate oxide. The effect of a forming gas annealing (FGA) process on the gate oxide traps was also analyzed with LF noise and compared with that of ETA. Although electrical Joule heating was applied under a condition of ambient air, not hydrogen-rich atmosphere, the passivation effect was superior to that of a FGA process conducted in diluted H2 ambient.

Electro-Thermal Annealing Method for Recovery of Cyclic Bending Stress in Flexible a-IGZO TFTs

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) fabricated by low-temperature processes on a flexible substrate can easily be degraded by mechanical deformation. Furthermore, lower performance in terms of the initial characteristics and reliability levels compared to those fabricated on glass substrates with relatively high heat treatments is inevitable. To solve these problems, a local electro-thermal annealing (ETA) method was applied to flexible a-IGZO TFTs processed at low temperature to enhance the inferior initial characteristics and reliability under a bending state. The enhancement of the characteristics and reliability by ETA can be attributed to the reduction of defects related to the oxygen through a localized Joule heat treatment with an extremely short duration (~1 ms). In addition, the effectiveness of ETA to recovery from bending stress even under harsh cyclic bending operation (strain condition of 0.833%) is verified.

Electrothermal Annealing of Catalytic Platinum Microwire Electrodes: Towards Membrane‐Free pH 7 Glucose Micro‐Fuel Cells

AbstractSurface activation and cleaning of platinum micro‐wires of 25 micron diameter has been achieved by a short one‐second electrothermal annealing treatment in air at 0.3 A (to orange glow). Voltammetric data suggest a decrease in the electrochemically active surface area with annealing time and a change in surface structure towards the Pt(100) crystalline face. The impact of electrothermal annealing on the electrocatalytic activity towards (i) oxygen reduction and (ii) glucose oxidation in pH 7 phosphate buffered aqueous solutions is investigated. In contrast to as‐received platinum, annealed platinum produces an electrocatalytic response towards glucose oxidation with increasing glucose concentration. A short one‐second anneal step is just as effective in enhancing catalysis as prolonged electrochemical cleaning in sulphuric acid. Finally, by combining a non‐annealed and an annealed microwire electrode, a very simple membrane‐free micro‐fuel cell system is devised operating in phosphate buffer at pH 7 with linearly increasing power output reaching 2.2 nW cm−2 for high glucose levels of 0.5 M.

Electrothermal Annealing (ETA) Method to Enhance the Electrical Performance of Amorphous-Oxide-Semiconductor (AOS) Thin-Film Transistors (TFTs).

An electro-thermal annealing (ETA) method, which uses an electrical pulse of less than 100 ns, was developed to improve the electrical performance of array-level amorphous-oxide-semiconductor (AOS) thin-film transistors (TFTs). The practicality of the ETA method was experimentally demonstrated with transparent amorphous In-Ga-Zn-O (a-IGZO) TFTs. The overall electrical performance metrics were boosted by the proposed method: up to 205% for the trans-conductance (gm), 158% for the linear current (Ilinear), and 206% for the subthreshold swing (SS). The performance enhancement were interpreted by X-ray photoelectron microscopy (XPS), showing a reduction of oxygen vacancies in a-IGZO after the ETA. Furthermore, by virtue of the extremely short operation time (80 ns) of ETA, which neither provokes a delay of the mandatory TFTs operation such as addressing operation for the display refresh nor demands extra physical treatment, the semipermanent use of displays can be realized.