Abstract
Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In order to maximize power efficiency during electro-thermal annealing (ETA), applying gate module engineering was more suitable than engineering the isolation or source drain modules.
Highlights
MOSFETs have been aggressively scaled down to improve packing density and chip performance [1]
short-channel effects (SCEs) have been effectively suppressed by improving gate controllability with three-dimensional (3D) device structures such as FinFETs and gate-all-around (GAA) FETs, and high-k gate dielectric and metal gate (HKMG)
Degradation in the transconductance subthreshold swing (SS) and V T were observed at 227 mV/dec and 0.65 V, respectively
Summary
MOSFETs have been aggressively scaled down to improve packing density and chip performance [1]. As semiconductor devices shrunk, several issues have arisen, such as short-channel effects (SCEs). SCEs give rise to an increase in the off-state current (IOFF ) and subthreshold swing (SS) and result in an increase in static power consumption (POFF = V DD × IOFF ) in the OFF-state. SCEs have been effectively suppressed by improving gate controllability with three-dimensional (3D) device structures such as FinFETs and gate-all-around (GAA) FETs, and high-k gate dielectric and metal gate (HKMG). Gate dielectric damage from hotcarrier injection (HCI), which is associated with the lateral drain electric field, has resurfaced as a matter of concern in semiconductor devices [2,3]. HCI increases both the threshold voltage (V T ) and SS, and results in unwanted V T mismatching while increasing IOFF in circuitries. The HCI decreases both the ON-state current (ION )
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