Electrostatic Discharge Stress Research Articles

Diode String With Reduced Clamping Voltage for Efficient On-Chip ESD Protection

The standard steps of P− implantation and silicide block in the complementary metal-oxide semiconductor (CMOS) process are used in this design to implement the proposed diode string. The novel diode string realized by the diodes of P+ with N-well (P+/NW) and P− with N+ (P−/N+) is proposed in this letter. Besides, two diodes are merged together to form a silicon-controlled rectifier path to reduce the clamping voltage during electrostatic discharge (ESD) stress. The test devices of prior and proposed diode strings have been compared in a 0.18 ${\mu }\text{m}$ CMOS process. With the higher current-handling ability and lower clamping voltage, the proposed diode string can be used as the efficient on-chip ESD protection device.

CDM-Reliable T-Coil Techniques for a 25-Gb/s Wireline Receiver Front-End

An inherent CDM–electrostatic discharge (ESD) hazard exists in T-coil circuits due to magnetic coupling from the pad to the receiver input. An “inductance halving” technique is proposed to reduce magnetic coupling during ESD, thereby canceling voltage overshoot. Receiver circuits with continuous-time linear equalizers are placed on a 65-nm CMOS test chip to evaluate the performance of the proposed T-coil in comparison with the conventional T-coil with secondary ESD protection. From the eye diagram test using 25-Gb/s pseudorandom bit sequence data, the receiver with an inductance-halving T-coil shows 1.8× higher and 29% wider eye opening, as compared with the receiver with a T-coil protected by a secondary ESD device. In a very fast transmission line pulsing test, both schemes achieve around an 8-A failure current, which demonstrates that the proposed T-coil can effectively protect receiver circuits against CDM-like ESD stresses.

Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High- $k$ Metal Gate CMOS Process

To effectively protect integrated circuits from electrostatic discharge (ESD) damage, this letter proposes a silicon-controlled rectifier (SCR) device with low trigger voltage, low leakage current, low parasitic capacitance, and which requires no additional process step. The proposed device uses two metal gates to separate the anode and cathode of the SCR to reduce the leakage current. These two gates are well controlled to trigger the SCR device. The test devices have been implemented and verified in a 28-nm high- $k$ metal gate CMOS process. Experimental results show that the proposed SCR exhibits a low trigger voltage ( 1 kV in human-body-model tests). Based on its good performances during ESD stress and normal circuit operating conditions, the proposed SCR device is very suitable for ESD protection in advanced CMOS processes.

A New Method to Estimate Failure Temperatures of Semiconductor Devices Under Electrostatic Discharge Stresses

Thermal runaway is one of the main causes of semiconductor device failure under electrostatic discharge (ESD) stresses. An experimental method to investigate the failure temperature under such electrical stresses is proposed. By extrapolating the power-to-failure under different stress time versus ambient temperature curves to the temperature axis, an effective failure temperature is extracted which represents the real failure temperature. This temperature is observed to be higher than the temperature at which the semiconductor becomes intrinsic. The latter is conventionally regarded as the critical temperature for thermal failure. These findings suggest that a different thermal-related mechanism is responsible for the ESD-induced damage in semiconductor devices.

Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress**Project supported by the Beijing Municipal Natural Science Foundation, China (Grant No. 4162030) and the National Science and Technology Major Project of China (Grant No. 2013ZX02303002).

The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier (DTSCR) is presented in this paper. Combined with the device simulation, a mathematical model is built to get a more in-depth insight into this phenomenon. The theoretical studies are verified by the transmission-line-pulsing (TLP) test results of the modified DTSCR structure, which is realized in a 65-nm complementary metal–oxide–semiconductor (CMOS) process. The detailed analysis of the physical mechanism is used to provide predictions as the DTSCR-based protection scheme is required. In addition, a method is also presented to achieve the tradeoff between the leakage and trigger voltage in DTSCR.

Characteristics of ESD protection devices operated under elevated temperatures

In this paper, characteristics of electrostatic discharge (ESD) protection devices operating under ESD stress and various ambient temperatures are investigated. The devices considered are a P+/NW diode and several silicon controlled rectifiers (SCRs) including Lateral SCR (LSCR), Modified Lateral SCR (MLSCR), No Snapback SCR (NS-SCR), Low Voltage Triggering SCR (LVTSCR), and P-Substrate Triggered SCR (PSTSCR) fabricated in a 0.35μm BCD (Bipolar-CMOS-DMOS) technology. Measurements are conducted using the Barth 4002 transmission line pulse (TLP) tester and the Signatone S1060 heating module, and the TLP I–V characteristics are analyzed in details. TCAD simulation is carried out and underlying physical mechanisms related to the effect of temperature on key ESD parameters are provided.

Large‐scale transient electrical‐thermal co‐simulation of interconnects under electromagnetic pulses

ABSTRACTThe electrical‐thermal co‐simulation is employed to analyze the transient electrical and thermal behaviors of large‐scale on‐chip and 3‐D interconnects. The analyses are performed when the interconnects are exposed to electromagnetic pulses in order to simulate both self‐heating effects under normal working conditions and thermal breakdowns under electrostatic discharge stresses. The impact of power maps on the transient thermal responses under the electrostatic discharge stress is also studied. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2559–2563, 2016

Quad-SCR Device for Cross-Domain ESD Protection

A new electrostatic discharge (ESD) protection device, called quad-silicon controlled rectifier (QSCR), is proposed and verified in a 0.25- $\mu \text{m}$ CMOS process. The QSCR is designed to be used as ESD protection between separated power domains. Since the QSCR embeds four SCRs between its four terminals, no extra ESD clamps are needed to protect the interface circuits between two separated power domains. Implementations with different circuit topologies were also analyzed to achieve a comprehensive ESD protection design for different applications. From the experimental results, the QSCR can withstand 8-kV HBM and 600-V MM ESD stresses with a silicon area of 75 $\mu \text {m} \times 100~\mu \text{m}$ .

A Novel Cascade-Free 5-V ESD Clamp Using I-MOS: Proposal and Analysis

In this paper, we present a new ESD device using the p-channel impact ionization MOSFET (I-MOS) with its gate and source connected to the ground, and its drain connected to the input/output (I/O) pad, called as the gate grounded I-MOS (GGIMOS). The proposed GGIMOS uses the conventional thick oxide (used for 2.5-V I/O devices) for 5-V failsafe/fault-tolerant I/O applications. For positive electrostatic discharge (ESD) stress, the turn-on mechanism is through controlled avalanche multiplication. During negative stress, the GGIMOS acts as a forward-biased gated diode. The gate oxide reliability concern of the p-channel I-MOS is alleviated by implementing the device in the p-substrate instead of n-well. The physics and operation of the GGIMOS is explained using electrothermal technology computer-aided design simulations and its performance is benchmarked using the simulated transmission line pulsing (TLP), very fast TLP, and human body model results. The proposed device eliminates the need for: 1) a cascaded nMOS architecture for high-voltage capability; and 2) a return diode for negative ESD stress conditions resulting in an area-efficient ESD clamp design. This makes the GGIMOS a potential device for ESD clamping applications in the state-of-the-art CMOS technologies.

ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC

For high-voltage (HV) applications, the electrostatic discharge (ESD) protection design using a traditional HV device, such as laterally diffused MOSFETs, usually consumes large silicon area to meet sufficient ESD specification. In this paper, an area-efficient ESD protection design with stacked high-holding-voltage silicon-controlled rectifier (HHVSCR) is proposed and verified in a 0.25- $\mu \text{m}$ 5/60 V Bipolar-CMOS-DMOS process. The proposed HHVSCR is fabricated in low-voltage wells and has the characteristics of HHV and high failure current with the same silicon area as the traditional SCR. From the experimental results, the proposed HHVSCR stacking structure can fit the desired ESD protection design window for the 60 V pins of a battery-monitoring IC and successfully protect these 60 V pins against 7-kV human-body-mode ESD stress.

Trigger voltage walk-out phenomenon in SOI lateral insulated gate bipolar transistor under repetitive electrostatic discharge stresses

Trigger voltage walk-out phenomenon is found in SOI LIGBT’s under repetitive ESD stresses. Such a characteristic would cause an IC to be susceptible to the risk of exceeding the ESD design window and thus resulting in core circuit damages when the LIGBT is served as an ESD protection device in the SOI process. This trigger-voltage walk-out phenomenon is investigated in this paper, and both the experimental evidences and device simulation results are presented to offer the insight of the underlying physical mechanism.

Cathode Side Engineering to Raise Holding Voltage of SCR in a 0.5-㎛ 24 V CDMOS Process

A set of novel silicon controlled rectifier (SCR) devices’ characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (γ) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2- dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard 0.5-μm 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What’s more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.

Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28nm and 40nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87mA/μm to the highest 5.41mA/μm. Under 40nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83mA/μm to 8.79mA/μm and 29.78mA/μm, respectively.

Compact Thermal Failure Model for Devices Subject to Electrostatic Discharge Stresses

A leading cause of device failure under electrostatic discharge stress conditions is thermal failure. This failure occurs as a result of excessive energy dissipation which raises the temperature of the device to a critical breaking level. To predict such a physical failure at circuit level, a compact model compatible with circuit simulators is proposed. The model is derived from the fundamental heat transfer equations and is shown to accurately predict thermal failure for arbitrary electrical stress waveforms.

20 GHz on-chip measurement of ESD waveform for system level analysis

Reliability of embedded electronic products is a challenging issue regarding ElectroStatic Discharge (ESD) events into real live applications. This is strongly related to the increased number of embedded systems and to technologies shrinking that result in less robust chips. To ensure the safety of electronic systems, the ESD events have to be taken into account at first design phase. But equipment manufacturers are facing the dilemma that no information is provided by the semiconductor manufacturers. At the same time Integrated Circuit (IC) designers have to take into account the final application environment to build the ESD protection strategy. Depending on the external components (external means around the chip) the on-chip current path could change. Understanding how the system environment impacts the current path within the chip is needed. This paper deals with on-chip oscilloscope developed for in-situ measurement of real ESD event in 65nm CMOS technology. The measurement bandwidth of the embedded sampler is 100GHz, and 20GHz for the probes. Thanks to this technique, impact of the system on the current path of the on-chip ESD strategy will be observed. Some measurement results during an ESD stress on an I/O structure will be presented and analyzed showing that PCB trace and package induce the creation of new current paths.

SCR 기반 양방향성 ESD보호회로의 설계 변수 변화에 따른 전기적 특성의 관한 연구

본 논문에서는 높은 홀딩 전압을 갖는 SCR(silicon-controlled rectifier)기반 양 방향성 ESD 보호회로를 제안하였다. 일반적인 ESD 보호회로와 달리 양방향의 ESD Stress mode의 방전경로를 제공하며 높은 홀딩전압으로 latch-up면역 특성을 갖어 효과적인 ESD보호를 제공한다. 또한, 높은 홀딩전압을 위한 설계변수인 Gate Length와 N+bridge Length의 길이 변화에 따른 시뮬레이션을 Synopsys사의 TCAD 시뮬레이터를 사용하여 확인 하였다. 시뮬레이션 결과 2.1V에서 6.5V까지 홀딩 전압의 증가로 latch-up 면역 특성을 개선 하였으며, 기존 SCR보다 6.5V의 낮은 트리거 전압특성을 갖고 있어 제안된 ESD 보호 회로는 5V 이상의 공급전압을 갖는 application에 적용 가능하다. In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.

Compact failure modeling for devices subject to electrostatic discharge stresses – A review pertinent to CMOS reliability simulation

This paper reviews the physical mechanisms and compact modeling approaches of two physical damages in MOS devices induced by electrostatic discharge (ESD) stresses; namely gate oxide breakdown and thermal failures. Theories underlying the failure mechanism are discussed and compact models that can be used to monitor ESD induced gate oxide breakdown and thermal failure are developed. Related work reported in the literature is discussed, and benchmarking of measurement data versus simulation results are included in support of the modeling work.

Improving the Electrostatic Discharge Robustness of a Junction Barrier Schottky Diode Using an Embedded p-n-p BJT

The high-voltage (H-V) junction barrier Schottky (JBS) diode is often incorporated into the input or output of H-V integrated circuits. When the chip is connected to the external environment, it inevitably suffers electrostatic discharge (ESD) stress. However, the JBS diode can only withstand the forward-mode ESD but it is highly vulnerable to reverse-mode ESD. In this letter, a new kind of JBS diode that is incorporated with a p-n-p bipolar is developed. The experimental results demonstrated that the new device can improve the failure threshold voltages of the human body mode and machine mode by at least four times. The area increase for the new device is 2.2%.

Miscorrelation Between Air Gap Discharge and Human Metal Model Stresses Due to Multi-Finger Turn-On Effect

Operation of NLDMOS-SCR devices under the human metal model (HMM) and IEC air gap electrostatic discharge (ESD) stresses has been studied based on both the pulsed measurements and mixed-mode simulations. Under the IEC air gap testing, the devices are found to suffer the non-uniform multi-finger turn-on behavior and hence a relatively low passing level, whereas both the IEC contact and HMM stresses do not give rise to such an adversary effect and result in a considerably higher passing level. It is further shown that the non-uniform multi-finger turn-on effect depends on the stress pulse rise time. Such dependence has also been examined and verified using the transmission line pulsing (TLP) technique with rise times ranging from 10 to 40 ns.

Effects of Electrostatic Discharge Stress on Current-Voltage and Reverse Recovery Time of Fast Power Diode

Fast recovery diodes (FRDs) were developed using the <TEX>$p^{{+}{+}}/n^-/n^{{+}{+}}$</TEX> epitaxial layers grown by low temperature epitaxy technology. We investigated the effect of electrostatic discharge (ESD) stresses on their electrical and switching properties using current-voltage (I-V) and reverse recovery time analyses. The FRDs presented a high breakdown voltage, >450 V, and a low reverse leakage current, < <TEX>$10^{-9}$</TEX> A. From the temperature dependence of thermal activation energy, the reverse leakage current was dominated by thermal generation-recombination and diffusion, respectively, at low and high temperature regions. By virtue of the abrupt junction and the Pt drive-in for the controlling of carrier lifetime, the soft reverse recovery behavior could be obtained along with a well-controlled reverse recovery time of 21.12 ns. The FRDs exhibited excellent ESD robustness with negligible degradations in the I-V and the reverse recovery characteristics up to <TEX>${\pm}5.5$</TEX> kV of HBM and <TEX>${\pm}3.5$</TEX> kV of IEC61000-4-2 shocks. Likewise, transmission line pulse (TLP) analysis reveals that the FRDs can handle the maximum peak pulse current, <TEX>$I_{pp,max}$</TEX>, up to 30 A in the forward mode and down to - 24 A in the reverse mode. The robust ESD property can improve the long term reliability of various power applications such as automobile and switching mode power supply.