Diode String With Reduced Clamping Voltage for Efficient On-Chip ESD Protection

Abstract

The standard steps of P− implantation and silicide block in the complementary metal-oxide semiconductor (CMOS) process are used in this design to implement the proposed diode string. The novel diode string realized by the diodes of P+ with N-well (P+/NW) and P− with N+ (P−/N+) is proposed in this letter. Besides, two diodes are merged together to form a silicon-controlled rectifier path to reduce the clamping voltage during electrostatic discharge (ESD) stress. The test devices of prior and proposed diode strings have been compared in a 0.18 ${\mu }\text{m}$ CMOS process. With the higher current-handling ability and lower clamping voltage, the proposed diode string can be used as the efficient on-chip ESD protection device.