A New Method to Estimate Failure Temperatures of Semiconductor Devices Under Electrostatic Discharge Stresses

Abstract

Thermal runaway is one of the main causes of semiconductor device failure under electrostatic discharge (ESD) stresses. An experimental method to investigate the failure temperature under such electrical stresses is proposed. By extrapolating the power-to-failure under different stress time versus ambient temperature curves to the temperature axis, an effective failure temperature is extracted which represents the real failure temperature. This temperature is observed to be higher than the temperature at which the semiconductor becomes intrinsic. The latter is conventionally regarded as the critical temperature for thermal failure. These findings suggest that a different thermal-related mechanism is responsible for the ESD-induced damage in semiconductor devices.