A Novel Cascade-Free 5-V ESD Clamp Using I-MOS: Proposal and Analysis

Abstract

In this paper, we present a new ESD device using the p-channel impact ionization MOSFET (I-MOS) with its gate and source connected to the ground, and its drain connected to the input/output (I/O) pad, called as the gate grounded I-MOS (GGIMOS). The proposed GGIMOS uses the conventional thick oxide (used for 2.5-V I/O devices) for 5-V failsafe/fault-tolerant I/O applications. For positive electrostatic discharge (ESD) stress, the turn-on mechanism is through controlled avalanche multiplication. During negative stress, the GGIMOS acts as a forward-biased gated diode. The gate oxide reliability concern of the p-channel I-MOS is alleviated by implementing the device in the p-substrate instead of n-well. The physics and operation of the GGIMOS is explained using electrothermal technology computer-aided design simulations and its performance is benchmarked using the simulated transmission line pulsing (TLP), very fast TLP, and human body model results. The proposed device eliminates the need for: 1) a cascaded nMOS architecture for high-voltage capability; and 2) a return diode for negative ESD stress conditions resulting in an area-efficient ESD clamp design. This makes the GGIMOS a potential device for ESD clamping applications in the state-of-the-art CMOS technologies.