Abstract
For the first time, this paper reports the quasi-static behavior and the applicability of the tunnel field effect transistor (TFET) for the on-chip electrostatic discharge (ESD) protection. ESD evaluations are performed on 28-nm fully depleted silicon-on-insulator (FDSOI), bulk TFET and compared with conventional shallow trench isolation (STI) diode using a well calibrated 3-D technology computer aided design (TCAD) device and process simulation deck. Initial design insights are obtained using the DC characteristics. The quasi-static behavior of a TFET is studied by applying transmission line pulsing (TLP) and very fast TLP (VFTLP) pulses at its drain terminal with gate shorted together and source connected to the ground. During negative TLP pulse at the drain, the TFET becomes a forward biased gated diode and exhibits reduced on-resistance compared to the STI diode. During positive TLP pulse, the tunneling current at the source-channel junction introduces a low impedance current path from drain to source compared to the blocking behavior of the STI diode. A short description of the advantages and challenges of the TFET from ESD perspective are also discussed. Finally, a new TFET ESD network is proposed and shown to exhibit multiple current paths compared to STI diode-based ESD network. From the network simulations, the proposed TFET-based ESD network is shown to exhibit better CDM response and hence providing a robust ESD solution for future system-on-chip design.
Highlights
Developing a robust electrostatic discharge (ESD) network in the advanced complementary metal oxide semiconductor (CMOS) technologies is quite challenging because of the reduced off-state breakdown voltages, gate oxide breakdown and safe operating area (SOA) of the load to be protected
DC CHARACTERISTICS The transfer characteristics gives an estimate of the offcurrent and the on-current required for calculating the parasitic leakage current at the input/output I/O pad during the functional operation
Since tunnel field effect transistor (TFET) is leaky compared to the shallow trench isolation (STI) diode, we have analyzed its behavior with varying gate lengths and bias voltages are explained
Summary
Developing a robust electrostatic discharge (ESD) network in the advanced complementary metal oxide semiconductor (CMOS) technologies is quite challenging because of the reduced off-state breakdown voltages, gate oxide breakdown and safe operating area (SOA) of the load to be protected This results in a narrow ESD design window [1]. Though there is a continuous research on-going to reduce the on-chip HBM and CDM standards from 2 kV to 1 kV and 500 V to 250 V respectively by implementing ESD control measures during manufacturing environment without affecting the yield, the proposal has not been accepted as the ESD standard across various semiconductor original equipment manufacturers (OEM) and the ESD targets remains unaltered with device scaling This motivated us to evaluate the novel device architectures and networks in state of the art CMOS technologies. Understanding ESD response of the TFET is important for
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