Electrostatic Discharge Stress Research Articles

Principle and verification of behavior model of gate-controlled SCR with adjustable on-resistance

This paper delineates the implementation of a gate-controlled Silicon Controlled Rectifier (SCR) behavioral model using Cadence software. The model is designed to tackle the absence of gate-control effect characteristics in extant models. This enables more precise simulation of the snapback behavior of such gate-controlled SCR devices under electrostatic discharge (ESD) stress. This work fabricates three types of SCR devices: Traditional SCR(T-SCR), Single-Gate SCR (SG-SCR), and a Double-Gate SCR (DG-SCR). These devices are fabricated using the 0.18 μm CMOS process and varied in the number of gates. The physical principles of the device are validated through two-dimensional electrical simulations. Furthermore, the model results are confirmed by the transmission line pulse (TLP) test results of the final device. The results demonstrate that the simulation results of the gate-controlled SCR behavioral model fit the TLP test results of the three SCR devices. The model’s applicability across different number of fingers devices confirms its scalability. Further, the model was simulated with the HBM equivalent circuit, and the comparison with the actual results confirmed the model’s applicability to HBM simulation.

Electrostatic discharge induced degradation of optical-electrical properties and defect evolution of GaAs-based oxide-confined VCSELs.

GaAs-based oxide-confined vertical-cavity surface-emitting lasers (VCSELs) exhibit relatively low resistance against reliability-related damage. In order to gain a deeper understanding of the degradation and failure mechanism in oxide-confined VCSELs caused by electrostatic discharge (ESD)-induced defect proliferation, we investigated the effects of ESD stress on the degradation of optical-electrical characteristics and the evolution of defects in VCSELs under human body model test condition. The degradation threshold values for forward and reverse ESD pulse amplitudes were estimated to be 200 V and -50 V, respectively. Notably, VCSELs demonstrated greater sensitivity to reverse bias ESD compared to forward bias ESD. Analysis of optical emission and microstructure provided evidence that the device failure is attributed to an increase in ESD current density, leading to the multiplication of dark line defects (DLDs) originating from the edge of the device's oxide aperture. The formation of defects occurred suddenly in discrete events within small regions, rather than progressing gradually and uniformly. These defects propagated and led to damage across the entire active region. We believe that our results would be meaningful for improving the reliability of VCSEL in the future.

Improved SEED Modeling of an ESD Discharge to a USB Cable

Integrated circuits (ICs) connected to a universal serial bus (USB) interface require robust electrostatic discharge (ESD) protection strategies due to the nature of the high-speed interface and the regular access by users. System-efficient ESD design (SEED) simulations can help predict the level of ESD stress seen by the IC when protected by a transient voltage suppressor (TVS). In the following paper, previously developed models were improved to predict the voltage and current seen by a TVS and an on-chip protection diode when an ESD gun was discharged to one USB cable pin. Models were improved, in part, by accurately modeling the conductivity modulation within the behavioral TVS model and by using a measured equivalent source to represent the complex interaction between the ESD gun, USB cable, and enclosure. The response of the TVS and on-chip diode was studied in simulation and measurement for several cable configurations and when adding passive components between the TVS and on-chip diode. Simulations predicted peak and quasi-static voltages and currents at the TVS and on-chip diode within 30% of those seen in measurements. The proposed modeling process can help engineers to evaluate and optimize the effectiveness of their ESD protection strategies under complicated test conditions.

Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors

The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.

A Novel Segmented LDMOS-SCR Structure With 8-kV HBM ESD Robustness in CMOS Analog Multiplexer

A novel segmented laterally diffused MOS embedded silicon-controlled rectifier (SCR) structure, called NSLDMOS-SCR, is proposed and verified in an optimal 5-V/40-V bipolar CMOS DMOS (BCD) process. Superior to the strip LDMOS-SCR, the proposed NSLDMOS-SCR exhibits a high holding voltage of 20.6 V and an excellent failure current of 12.2 A in a width of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$200~\mu \text{m}$ </tex-math></inline-formula> , benefitting from the widened segmented topology of the source and body. As such, for ±15-V circuit application, the NSLDMOS-SCR can fit the electrostatic discharge (ESD) design window for an eight-channel CMOS analog multiplexer and effectively protect these pins against 8-kV human-body-mode ESD stress.

Editorial Introduction to the Special Issue on Electrostatic Discharge and Immunity—From IC to System

The papers in this special issue focus on scientific contributions in the field of electrostatic discharge (ESD) and immunity—from integrated circuits (ICs) to system. ESD can damage or disrupt electronic systems. With continued scaling of ICs, a combined approach of IC and system forms the best path for understanding and ensuring robustness. This relates to the IC itself: input/output (I/O) structures, power distribution network (PDN), interfaces between IP blocks, as well as the interaction of external protection devices with internal ESD protection structures during system level stress. To effectively protect the ICs fabricated in the advanced nanoscale CMOS processes, the turn-on speed of ESD protection devices must be enhanced to quickly discharge ESD current before the internal circuits are damaged by ESD stresses. Not only component level ESD events, the system level ESD test specified in the IEC 61000-4-2 standard has been used to verify ESD immunity of the microelectronics products. During system level ESD testing, the ESD problems relates to soft failures. So far, only few models for soft failures have been reported. It becomes visible that well designed hard failure protection can also reduce the likelihood of soft failures as most of the current is diverted from the IC and will not disturb the PDN of the IC. ESD robustness in the system level and component level are both important to meet the electromagnetic compatibility (EMC) regulations and/or standards in the industry.

A Standalone Graph-Theory Based Tool for Full-Chip ESD Verification

In this article, a novel flow of the automatic electrostatic discharge (ESD) verification is presented. A basic overview of the most important methodology steps is shown, with more detailed explanation of breaking voltage (BV) model generation. Based on transmission line pulsing measurements, the BV models are used for modeling devices under ESD stress conditions. The principle behind the custom-made tool ESDh is disclosed. Being based on graph-theory algorithm, specifically the Floyd-Warshall algorithm, the tool detects and reconstructs current paths between any node-to-node pair of the integrated circuit (IC). In addition, ESDh can calculate the full current-voltage (IV curve) of any current path. Consequently, this approach is able to find failing paths, failing devices, and failing levels of tested IC. As the method in this work uses the full netlist, without dismissing the core circuitry, ESDh can be used for verifying the self-protection levels of the IC.

Design of compact-diode-SCR with low-trigger voltage for full-chip ESD protection

In this article, a compact-diode-silicon-controlled rectifier (CDSCR) for full-chip electrostatic discharge (ESD) protection is proposed and verified in 0.18 μm Silicon-on-Insulator (SOI) Bipolar-CMOS-DMOS (BCD) process. Intrinsic parasitic SCRs and diodes are employed as the main ESD paths, which greatly reduces area consumption. Besides, due to the RC- triggered circuit, low trigger voltage and short turn-on time are realized. With equivalent circuit and two-dimensional (2D) technology computer-aided design (TCAD) simulation, the operation principle and working mechanism are analyzed. In addition, transmission line pulse (TLP) and very fast TLP (VF-TLP) testing results show that the CDSCR could can endure human body model (HBM) pulse of 3420 V without latch-up issue and protect the chip effectively in charge device model (CDM) event. Furthermore, the proposed structure exhibits high current handing ability during ESD stress conditions and sufficiently low leakage current during normal circuit operating conditions. The CDSCR is conformed to provide full-chip ESD protection for 1.2 V application.

A power supply clamp with self-cutoff the conducted ESD current path mechanism for latch-up free

A power supply clamp with self-cutoff the conducted ESD (electrostatic discharge) current path mechanism for on-chip ESD protection is developed by TCAD simulation and experiments. The proposed clamp consists of SCR (silicon controlled rectifier) acting as ESD protection device between power and ground rail, and control circuit generating cutoff signal. Different from the traditional SCR which increases holding voltage to prevent latch-up, the proposed structure can automatically set block to cut off the conducted SCR after triggered by ESD stress. Simulation analysis and experimental results show that the reported structure presents self-cutoff capability and latch-up free characteristic even under power-on case.

Optimization on Bi-Directional PNP ESD Protection Device for High-Voltage FlexRay Applications

The I/O of CMOS integrated circuits of for FlexRay communication has to be tolerant with the input signals of ±60 V in its normal applications. Thus, the on-chip electrostatic discharge (ESD) protection devices for such I/O pin must be kept off unless the bus voltage is higher than 60 V or lower than −60 V. In this work, the bi-directional p-n-p (Bi-PNP) device was proposed and optimized for bi-directional ESD protection in the FlexRay communication systems. The proposed Bi-PNP devices were verified in a 0.15- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD technology. The relationships between the layout spacing of doping layers and other device characteristics, including trigger voltage (Vt1) and breakdown voltage (BV), were investigated, respectively. The size dependence on the ESD robustness was also studied. The transient response of the proposed Bi-PNP device under fast ESD stress was investigated by very fast TLP (vf-TLP) and TLP measurement. In addition, the empirical correlations of the It2 on the HBM and IEC 61000-4-2 failure levels were estimated. Finally, the recommended size and parameters of the proposed Bi-PNP device for ±60 V FlexRay application are provided.

Dynamic electrostatic-discharge path investigation relied on different impact energies in metal–oxide–semiconductor circuits

Gate-grounded n-channel metal–oxide–semiconductor (GGNMOS) devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction, easy triggering, and low power dissipation. We present a novel I–V characterization of the GGNMOS used as the power clamp in complementary metal–oxide–semiconductor circuits as a result of switching the ESD paths under different impact energies. This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground, and thus should be urgently analyzed and resolved. Transmission-line-pulse, human-body-modal, and light-emission tests were performed to explore the root cause.

All-HKMG-bounded SCR for advanced ESD protection in 14 nm FinFET technology

In this paper, a novel all-high-K metal gate (HKMG)-bounded silicon-controlled rectifier (AHBSCR) is proposed for advanced electrostatic discharge (ESD) protection in FinFET processes. Depart from its prior arts, in AHBSCR, both the main SCR path and the triggering diode path are placed along the Fin direction, and all active areas are bounded by HKMG, thus expressing superior conduction capability under various ESD stresses and a more compact silicon footprint. Experimental results show that the proposed AHBSCR owns a suitable snapback window of 1.1 V–1.6 V, a fast turn-on speed of only 400 ps, an extreme low leakage current of less than 100 pA@-1 V as well as a figure of merit of 24.3 mA fF−1, indicating it is competent to replace the conventional FinFET diodes in rail-based ESD network to further improve the efficiency of ESD protection.

Conductive Oxides for Formulating Mitigated-Sensitivity Energetic Composite Materials

Composite energetic nanomaterials, otherwise known as nanothermites, consist of physical mixtures of fuel and oxidizer nanoparticles. When a combustion reaction takes place between both components, extremely impressive conditions are created, such as high temperatures (&gt;1000 °C), intense heat releases (&gt;kJ/cm3), and sometimes gas generation. These conditions can be adjusted by modifying the chemical nature of both reactants. However, these energetic composites are extremely sensitive to electrostatic discharge. This may lead to accidental ignitions during handling and transportation operations. This study examines the use of a n-type semiconductor ITO material as an alternative oxidizer combined with aluminum fuel. Indium tin oxide (ITO) ceramic is widely used in the elaboration of conducting coatings for antistatic applications because of its ability to conduct electrical charges (n-type semiconductor). The energetic performance of the Al/ITO thermite was determined, i.e., the sensitivity threshold regarding mechanical (impact and friction) and electrostatic discharge (ESD) stresses, as well as the reactive behavior (heat of reaction, combustion front velocity). The results demonstrate insensitivity toward mechanical stresses regardless of the ITO granulometry. As regards the spark sensitivity, using ITO microparticles considerably raises the sensitivity threshold value (&lt;0.21 mJ vs. 13.70 mJ). A combustion velocity of nearly 650 m/s was also determined.

ESD Stress Analysis and Suppression in a Single-Junction Thermal Converter

This article presents an outline of Electric Transient Disturbances (ETDs), represented by the ElectroStatic Discharge (ESD) in accordance with the Human-Body Model (HBM), on the AC-DC transfer measurement standard, represented by the Single-Junction Thermal Converter (SJTC) Thermal Element (TE). Mitigation technique against the power dissipation build-up, higher than the operational margins recommended by a manufacturer, on the TE were proposed and modelled using Laplace Transform (LT) analysis. A mathematical model and an optimization algorithm were developed to determine the equivalent circuit model parameters of a Transient Overload Protection Module (TOPM) that would offer adequate protection against destructive power dissipation levels build-up on the TE. The mathematical model was developed using an 8 kV ESD, which was expected to deliver short-circuit current with a peak value of approximately 5.33 A through a load impedance of approximately 1 m\varOmega. The ESD stress signal was injected into the TOPM connected in parallel with the TE. The active power dissipated by the SJTC TE per period of transient response was calculated from the current and voltage obtained from the mathematical analysis, and the results indicate a power dissipation of 10 mW by the TE. From the algorithm, the model parameter that noticeably influences the power dissipation capabilities of the TOPM is the inductance and it must be smaller than 1.2 nH. A CAD based simulation model was developed and analysed. The simulation results agreed with the mathematical model.

A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation

It is challenging to simulate the snapback behaviors under electrostatic discharge (ESD) stresses due to the limitation of simulation program with integrated circuit emphasis (SPICE) simulation tools. In this paper, a new model is proposed to investigate the avalanche breakdown effect using the voltage-controlled current source (VCCS), which greatly facilitates the calculation of the avalanche multiplication factor M and improves the convergence characteristics. In particular, this new method transfers the exponential relationship of M into the linear relationship of the VCCS gain. The versatility of the model is validated by its operations in various ESD protection circuits with MOS as the discharge device, while the scalability is demonstrated by its applications in varied device sizes.

Reliability Issues of Thin Film Transistors Subject to Electrostatic Discharge Stresses: An Overview (Adv. Electron. Mater. 2/2022)

Electrostatic Discharge Electrostatic discharge is one of the most prevalent threats to the reliability of electronic components. In article 2100886, Yan Yan, Juin J Liou, and co-workers provide an overview to summarize the existing articles on the topic of reliability issues of thin film transistors in different processes subject to electrostatic discharge stresses and discuss its current status and future research directions.

Novel dual-direction electrostatic discharge device with lateral PNP transistor

With the shrinking of semiconductor technology and the increasing of integrated circuits, electrostatic discharge (ESD) as a common natural phenomenon has become one of the main reasons for the failure and reliability reduction of electronic products in integrated circuits. A novel dual-direction ESD device (PNP_DDSCR) with embedded lateral PNP transistor is proposed for diminishing ESD damage. The response process and current transportation of PNP_DDSCR under different ESD stress modes are investigated. Comparative analyses between conventional DDSCR and PNP_DDSCR are executed by TCAD simulation. On the stage of device triggering, the embedded lateral PNP transistor inner DDSCR system provides triggering current for device. The injection efficiency of parasitic transistor in the DDSCR system is improved, and the positive feedback system is promoted. Thus, the holding voltage of PNP_DDSCR is higher than that of conventional DDSCR. At the same time, an extra triggering path introduced by embedded lateral PNP transistor of PNP_DDSCR makes the total triggering path of device shorten. Therefore, the transient overshoot voltage of PNP_DDSCR is lower than that of DDSCR. For thermal performance, most of the heat first accumulates near the lateral PNP transistor , and then the peak point of heat turns to main SCR path with the conduction of PNP_DDSCR. The heat accumulation in PNP_DDSCR is shared by the path of embedded lateral PNP transistor. As a result, the average temperature in PNP_DDSCR is lower than that in DDSCR and the ability of PNP_DDSCR to dissipate heat is more perfect. Comparing with DDSCR, the conclusions are obtained. Under the condition of transmission line pulse (TLP) test simulation analyses, the triggering voltage is reduced by 31%, the holding voltage is increased by 16.8%, the ESD design window is optimized by 44.5%, and on-resistance is lower. When TLP stress is 2.67 A, the average temperature of PNP_DDSCR is much lower than that of traditional DDSCR in the whole conduction process. With the increase of pulse lasting time, average temperature difference between two devices becomes great further. According to the very fast TLP (VF-TLP) testing results, clamping capability of PNP_DDSCR under transient overshoot voltage is more stable under the condition of fast turn-on speed. When the VF-TLP stress is 0.1 A, the overshoot voltage of PNP_DDSCR device is the 37% of that of DDSCR device while the PNP_DDSCR maintains a relatively fast triggering speed. Thus, the ESD protection capability of PNP_DDSCR is superior.

ESD Stress Effect on Failure Mechanisms in GaN-on-Si Power Device

This paper reports investigation of failure mechanisms of GaN-on-Si power device under electrostatic discharge (ESD) stress using on-wafer transmission-line pulse (TLP) testing. Hot-hole injections under the gate and filament formation in the buffer layer are examined by monitoring the threshold voltage (Vth) and on-resistance (Ron) subjected to a floating gate or an off-state gate voltage. Distinct and continued degradation has been observed after the ESD stress is removed indicating a slow de-trapping process due to deep-level buffer traps. Finally, 2D device simulation is used to probe the physical insight into failure mechanisms.

Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses

Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power management or noise isolation considerations. Besides, the fabricated transistors with thinner gate oxide for high-speed operation cause the ICs more sensitive to charged-device model (CDM) ESD events, especially under cross-domain stresses. The traditional cross-domain CDM ESD protection would result in some restrictions on circuit applications or cause some performance degradation. Thus, a new protection design with stacking footer/header metal-oxide-semiconductor (MOS) structure against cross-domain CDM ESD stresses was proposed in this work and verified in 0.18-μm CMOS technology. The proposed design got higher ESD robustness under CDM and HBM (human body model) ESD tests. Moreover, the CDM robustness of different stacking-MOS protection designs was also investigated in detail.

Analysis of Trap and Recovery Characteristics Based on Low-Frequency Noise for E-Mode GaN HEMTs Under Electrostatic Discharge Stress

The ESD effects on the E-mode AlGaN/GaN high-electron mobility transistors (HEMTs) with p-GaN gate are investigated under repetitive TLP pulses. Firstly, the degradation and recovery of output, transfer characteristics, gate-leakage characteristics and low-frequency noises (LFN) are analyzed in detail before and after reverse electrostatic discharge (ESD) stress. The experimental results show that the electrical characteristics of the devices gradually degraded as the transmission line pulse (TLP) pules increased. Subsequently, the LFN measurements are performed over the frequency range of 1 Hz–10 KHz by increasing TLP pulses. Finally, the recovery tendency of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DC</i> (direct current) characteristics and trap density are studied and discussed after resting the device at room temperature for 1 to 3 months. These results physically confirm that the mechanism of the performance degradation and recovery of the devices could be attributed to the trapping and releasing processes of electrons in the p-GaN layer and AlGaN barrier layer of AlGaN/GaN HEMTs, which change the electric field distribution under the gate.