Improved SEED Modeling of an ESD Discharge to a USB Cable

Abstract

Integrated circuits (ICs) connected to a universal serial bus (USB) interface require robust electrostatic discharge (ESD) protection strategies due to the nature of the high-speed interface and the regular access by users. System-efficient ESD design (SEED) simulations can help predict the level of ESD stress seen by the IC when protected by a transient voltage suppressor (TVS). In the following paper, previously developed models were improved to predict the voltage and current seen by a TVS and an on-chip protection diode when an ESD gun was discharged to one USB cable pin. Models were improved, in part, by accurately modeling the conductivity modulation within the behavioral TVS model and by using a measured equivalent source to represent the complex interaction between the ESD gun, USB cable, and enclosure. The response of the TVS and on-chip diode was studied in simulation and measurement for several cable configurations and when adding passive components between the TVS and on-chip diode. Simulations predicted peak and quasi-static voltages and currents at the TVS and on-chip diode within 30% of those seen in measurements. The proposed modeling process can help engineers to evaluate and optimize the effectiveness of their ESD protection strategies under complicated test conditions.