Electrostatic Discharge Protection Circuit Research Articles

Characteristic parameter model and circuit‐level simulation of gate‐controlled dual direction SCR for on‐chip ESD protection

SummaryDual‐directional SCR (DDSCR) with bidirectional discharge paths and high robustness is widely employed for electrostatic discharge (ESD) protection in integrated circuits. However, the design and simulation of on‐chip ESD protection circuits for dual‐directional paths remain challenging due to a lack of relevant device models. This paper designs a Gate‐Controlled Dual‐Direction SCR (GDDSCR) for providing electrostatic discharge (ESD) protection in industry‐level temperature sensors. Furthermore, a new behavioral model is developed based on the GDDSCR for simulating ESD protection circuits along both forward and reverse paths. Experimental results demonstrate that the GDDSCR behavioral model accurately reproduces the IV characteristics observed in bidirectional transmission line pulse (TLP) tests. In addition, the equivalent circuit based on human body model (HBM) is used for transient simulation, and the accuracy of the model is verified by relevant HBM experiments. The proposed model allows the direct extraction of parameters such as trigger voltage (Vt1), holding voltage (Vh), and on‐state resistance (Ron) through TLP testing, facilitating easy application to other types of DDSCR devices.

Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit

Electrostatic discharge (ESD) and electromigration are critical issues that significantly impact the reliability of ICs. While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention, potentially compromising IC reliability. This work analyzes various types of metal with different lengths, widths, and angles commonly used in ESD protection circuits in the CMOS process. The objective is to observe their behavior under continuous ESD zapping. The ESD-induced electromigration of metallization in the CMOS process has been analyzed, and metal sensitivity to system-level ESD events has also been identified. It is also analyzed from the perspective of energy that the ESD energy that metal can withstand will decrease as the ESD voltage increases, which will be even more detrimental to the ESD reliability of ICs. The findings from this study aim to provide valuable insights for designing metal lines in ICs to enhance ESD protection.

On-chip ESD Protection Design Methodologies by CAD Simulation

Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs) . On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization, prediction, and verification become essential to advanced chip designs, which highly depends on CAD algorithm and simulation that has been a constant research topic for decades. This paper reviews recent advances in CAD-enabled on-chip ESD protection circuit simulation design technologies and ESD-IC co-design methodologies. Key challenges of ESD CAD design practices are outlined. Practical ESD protection simulation design examples are discussed.

Research on Optimal Design of Chip ESD Protection Circuit Based on CMOS Technology

A high frequency circuit based on ESD protection and a new type of power grounding clamp circuit are designed. The oblique edge interfinger diode is used to achieve the optimal design of layout and performance. The design of electrostatic discharge protection circuit and flowsheet were completed in Jazz0.18-micron silicon germanium BiCMOS process. The protection voltage of electrostatic discharge is 3000 V. Higher electrostatic protection level can be obtained by changing the bifurcation index of diode. Improved protection of up to 4500 volts can be achieved. Through the test of the chip, it is proved that the chip fully meets the design requirements and can realize various types of digital circuits.

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

In terms of sustainable power semiconductors, the embedding of an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) is an important aspect. In order for the semiconductor circuit to operate continuously or stably, a sufficient protection circuit against external surges must be configured. The purpose of this thesis is not only to effectively operate the low-dropout (LDO) regulator according to the load current, but to also secure high reliability against ESD situations by embedding an ESD protection circuit at the IC level. Moreover, the existence and nonexistence of an ESD protection circuit at the IC level is directly related to reliability. The proposed LDO regulator has high reliability against ESD situations using an embedded silicon controlled rectifier (SCR)-based ESD protection circuit in the I/O clamp and power clamp. The results revealed that the LDO regulator can not only effectively control the output voltage according to the load current, but it can also stably maintain the output voltage against the ESD surge. Moreover, the proposed LDO regulator with an embedded ESD protection circuit implemented in a 0.13 μm BCD process maintained an undershoot voltage of 21 mV and overshoot voltage of 19 mV for a load current of 300 mA.

π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology

CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications.

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures. In this paper, the mixed TCAD model of the ESD protection circuit is built and simulated, and the negative transmission line pulse (TLP) injection damage experiment is carried out on the CD4069UBC chip. The circuit model consists of three-dimensional shallow trench isolation (STI) diode TCAD models and a three-dimensional multi-gate Complementary Metal-Oxide-Semiconductor (CMOS) inverter TCAD model. Moreover, the TCAD modeling is based on a 0.25 μm technology node. Through the transient simulation of the electrothermal coupling, the electrical signal of the input and output nodes of the circuit and the distribution of the electrothermal parameters in the device are obtained. Moreover, by analyzing the simulation results, the physical phenomena and the mechanisms of interference and damage mechanism during TLP injection are explained. The location and type of diode damage in the TLP injection simulation results of the circuit model are consistent with the TLP experiment damage results. The proposed ESD protection circuit model and analysis method are beneficial to ESD robustness prediction and ESD soft damage analysis of IC.

Design of LDO Regulator With High Reliability ESD Protection Circuit Using Analog Current Switch Structure for 5-V Applications

The modern electronic device should be able to provide stable voltage and current under a variety of conditions. The LDO regulator used in the electronic device is a system that requires various voltages and load currents. This paper suggests to the LDO regulator with the high reliability ESD protection circuit that achieves low peak voltage through analog switch structure. The proposed LDO regulator has the function of detecting the output voltage fluctuations depending on the load via an analog switch structure and effectively controlling the peak voltage. In addition, as IC is miniaturized and integrated, circuit failures frequently occur in mobile devices using the low voltage due to electrostatic discharge (ESD). The proposed ESD protection circuit is placed on I/O and power lines to prevent the IC circuit from being destroyed from the inevitable ESD phenomenon. Therefore, in this paper, an ESD protection circuit was built into the LDO regulator to verify high reliability from ESD situations. It was verified that the high reliability of the IC can be improved through effective current discharge due to ESD surge. The proposed LDO regulator, implemented in a 0.13μm BCD process, achieves an undershoot voltage of 25 mV and an overshoot voltage of 28 mV for a load current of 300 mA.

Design of high reliability LDO regulator with NLRSCR based ESD protection circuit using dynamic feedback loop for low-voltage applications

Capacitor-less low dropout voltage regulator applied to the mobile devices consistently exposes the peak voltage, which can increase the power consumption. This study proposes a dynamic feedback loop of the LDO regulator that provides a function to stably control the peak voltage irrespective of the change of the load current. The performance of the chip layout was evaluated under conditions of an output voltage of 3 V, a battery input voltage of 3.3 to 4.5 V, and a load current of 350 mA. As a result, the peak voltage keeps an undershoot voltage of 30 mV and an overshoot of 33 mV along the load current. In addition, the demand for miniaturization and integration of ICs and the application of low voltage applications are increasing. Thereby, the circuit damage due to ESD (Electro Static Discharge) may happen frequently. This is a significant factor influencing the overall reliability related to productivity and stability. In this study, we confirmed that the proposed LDO regulator with the ESD protection circuit of the NLRSCR structure secures high reliability at low voltage.

Design of current detection LDO regulator with silicon controlled rectifier based electrostatic discharge protection circuit to provide optimized voltage and power for system‐on‐chip applications

Various levels of circuits and systems in the ultra-low nanometer fabrication process should be considered to implement a system-on-chip (SOC) application to reduce power consumption. This letter is intended to propose a current detection structure that supplies and discharges additional current along the load current to provide the optimized voltage and power for SOC applications. The proposed electrostatic discharge (ESD) protection circuit placed on the power line and I/O has improved the reliability by preventing the direct or indirect destruction of the internal integrated circuit (IC) due to ESD. In addition, the proposed low drop out (LDO) regulator for the low-voltage applications has combined an ESD protection circuit to secure the high reliability of the IC. The proposed LDO regulator is implemented with a 0.18-μm BCD process and is kept an undershoot voltage of 23 mV and an overshoot voltage of 25 mV for a load current of 200 mA.

A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation

It is challenging to simulate the snapback behaviors under electrostatic discharge (ESD) stresses due to the limitation of simulation program with integrated circuit emphasis (SPICE) simulation tools. In this paper, a new model is proposed to investigate the avalanche breakdown effect using the voltage-controlled current source (VCCS), which greatly facilitates the calculation of the avalanche multiplication factor M and improves the convergence characteristics. In particular, this new method transfers the exponential relationship of M into the linear relationship of the VCCS gain. The versatility of the model is validated by its operations in various ESD protection circuits with MOS as the discharge device, while the scalability is demonstrated by its applications in varied device sizes.

Novel ESD device design for STT-MRAM memory chip

An investigation of the influence of the magnetic field induced by electrostatic discharge (ESD) current on magnetic tunnel junction (MTJ) device is presented in the paper. The transient magnetic field generated by the ESD current is not considered in the traditional CMOS ESD protection strategy, which may be a reason of the degradation of the performance and the robustness of STT-MRAM. An ESD protection circuit of STT-MRAM is proposed in the paper, including the diode-based ESD devices, the filter circuit and the power clamp. Based on the waveform analysis of the three ESD standard test models, including HBM, MM and CDM, a filter circuit is added in the ESD device to decrease the influence of the high frequency components on the magnetic device. The diode-based ESD devices are integrated in the ESD structure, which is used for the ESD window of STT-MRAM for its low operating voltage. Based on the operation mechanism of the STT-MRAM, its ESD window allows a low operating voltage, thus the diode-based devices are chosen to be integrated in the ESD device. The distribution and magnitude of the magnetic field are studied in the paper. The results show that the ESD protection circuit of STT-MRAM can effectively suppress the magnetic field generated by the ESD current, hence increasing the stability of STT-MRAM. Under the influence of the HBM, MM and CDM events, the ESD disturbance probability of the MTJ device are 2.0 × 10−12, 5.8 × 10−9 and 1.1 × 10−12 respectively. The influence of the memory density and the distance between pads and memory array are also investigated in this paper. The ESD protection strategy proposed in the paper can be adopted for the future high performance STT-MRAM.

All-directional Electrostatic-discharge Protection Circuit with High Area-efficiency

This paper proposes a design for a wholechip all-directional electrostatic-discharge (ESD) protection circuit using a resistor-capacitor (RC) lateral insulated-gate bipolar transistor (LIGBT)-based 12 V power clamp and a silicon-controlled rectifier (SCR)-based 12 V input/output (I/O) clamp. The RC LIGBT-based power clamp detects pulses through an ESD detection circuit and applies a bias to the gate. Therefore, the proposed power clamp does not have snapback curve and has a low impedance during an ESD event. In addition, the structural characteristics of the proposed I/O clamp enable it to provide discharge paths for all four ESD discharge modes (PS, PD, NS, ND), and the clamp is more area efficient than conventional ESD protection circuits composed of gate-grounded n-type metal-oxide-silicon transistors or SCRs. Moreover, because floating regions are inserted in the I/O clamp and the clamp has a high holding voltage, the clamp design is resistant to latch-up, which is a critical drawback of snapback devices. Therefore, the proposed ESD protection circuit can effectively provide highly reliable protection to internal integrated circuits. The proposed circuit was fabricated using a 0.18 ㎛ bipolar-CMOS-DMOS process, and the electrical properties and ESD robustness of the circuit were verified through a transmission line pulse measurement method and human body model surge application tests.

Transient Analysis of ESD Protection Circuits for High-Speed ICs

Electrostatic discharge (ESD) failures in high-speed integrated circuits (ICs) cause critical reliability problems in electronic devices. Transient voltage suppressor (TVS) diodes are installed on high-speed I/O traces to improve system-level ESD protection. To protect the circuit, the majority of ESD current must flow into the external TVS diode rather than into the IC, but due to turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> behavior, the TVS diode may not snap back when needed and the IC's internal protection may take most of the current. These race conditions between the internal and external ESD protection circuits were investigated for a universal serial bus(USB) interface board. The transient turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> behavior of the on-chip and off-chip protection circuitry was characterized by measurements and by system efficient ESD design (SEED) simulations. The effect of transmission line pulses (TLP pulses) and power supply voltages of different sizes on the response of the protection circuitry were monitored and compared with SEED simulations. SEED models showed good agreement with measurements and were used to study the impact of passive components added to a high-speed trace or within the IC package on the ESD protection response. Results show the importance of properly accounting for the parasitic resistance and inductance between the on-chip diode and off-chip TVS diode, as well as the length of the transmission line when choosing the external TVS device. Results also show that testing must be performed using mid-level events to account for possible problems due to race conditions.

Silicon-controlled Rectifier-based Electrostatic Discharge Protection Circuit with Additional NPN Parasitic Bipolar Junction Transistor for 5-V Application

This paper proposes a novel protection circuit based on a silicon-controlled rectifier (SCR) to prevent electrostatic discharge (ESD) at low voltages. The proposed device consists of an additional NPN parasitic bipolar transistor operated via application of an N+ diffusion region and a well breakdown voltage, to reduce the high trigger voltage caused by the well breakdown voltage of the existing SCR structure. Furthermore, the proposed device exhibits an improved trigger voltage, holding voltage, and dynamic resistance component when compared with existing parasitic PNP bipolar transistors. The proposed ESD protection circuit was manufactured using a 0.18 μm bipolar-CMOS-DMOS; it exhibited a significant improvement in electrical characteristics such as trigger voltage (8.1 V) and holding voltage (3.55 V), according to the results of transmission line pulse measurement. Hence, it is deemed to be suitable for 5-V-class applications.

Input bias current reduction technique for operational amplifier in a standard CMOS technology

AbstractThis paper presents input bias current (Ibias) reduction technique for high impedance CMOS op‐amps with the proposed current compensation circuit to deal with the leakage current caused by Electro‐Static Discharge (ESD) protection circuit of the IC. High input impedance CMOS op‐amps are widely used for the application of high precision sensors with quite small input current. However, the leakage current of ESD protection circuit for op‐amp causes a nonideality error of the Ibias. Especially, the ESD leakage current increases drastically at the high temperature environment, and hence the Ibias of CMOS op‐amp also increased significantly. An ESD leakage current compensation circuit is introduced to reduce the Ibias of CMOS op‐amp. The prototype amplifier with the proposed current compensation circuit is designed and fabricated in standard 0.7 µm CMOS technology. Measurement results show that the Ibias is reduced to a 100 pA or less from a typical 2.3 nA at 150°C.

Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes

In the implanted biomedical devices, the silicon chips with monopolar stimulation design have been widely applied. To protect the negative-voltage pins of the implanted silicon chip from the electrostatic discharge (ESD) damage, the ESD protection circuit should be carefully designed to avoid any wrong current path under normal circuit operation with the negative voltage. In this article, a new power-rail ESD clamp circuit for the application with an operating voltage of −6 V has been proposed and verified in a 0.18- $\mu \text{m}$ 3.3-V CMOS process. The proposed circuit, realized with only 3.3-V nMOS/pMOS devices, is able to prevent the gate-oxide reliability issue under this −6-V application. With the proposed ESD detection circuit, the turn-on speed of the main ESD clamp device, which is a stacked-nMOS (STnMOS), can be greatly enhanced. The STnMOS with a width of $400~\mu \text{m}$ can sustain over 8-kV human body model (HBM) ESD stress and perform low standby leakage current of ~5.4 nA at room temperature under the circuit operating condition with −6-V supply voltage.

Adaptive Dielectric Thin Film Transistors-A Self-Configuring Device for Low Power Electrostatic Discharge Protection

Large area and flexible electronic systems are widely used in applications such as displays, image sensors, wearable electronics and energy harvesting systems. A key element in many of these systems is the electrostatic discharge protection circuit. The conventional protection circuit uses large aspect-ratio diode connected thin film transistors that offer a low resistance path to the surge current but also does the same to signals during normal system operation resulting in power loss. Here we describe as well as demonstrate the feasibility of a novel idea for electrostatic discharge protection involving an adaptive dielectric thin film transistor that self-configures itself to a low resistance state during an electrostatic discharge event and a high resistance state during normal operation without external control. This results in 1000–10000 times the power savings compared to diode connected TFTs.

Compact ESD Protection Design for CMOS Low-Noise Amplifier

A low-noise amplifier (LNA) is the input part of a radio frequency (RF) transceiver, which is vulnerable to electrostatic discharge (ESD). When ESD events occur, they may change the original characteristics of the LNA, such as gain decrease and noise figure (NF) increase. Dual diodes (DD) with MOS-based power clamp is a traditional on-chip ESD protection circuit, but it has disadvantages of large parasitic capacitance, large turn-on resistance, large layout area, and large leakage current. Therefore, a new compact ESD protection circuit is proposed, which uses stacked diodes with embedded silicon-controlled rectifier (SDeSCR) and SCR-based power clamp to protect the LNA. The proposed design has advantages of low parasitic capacitance, low clamping voltage, high ESD robustness, and compact layout area. In this work, the ESD protection circuit and the ${K}$ -band LNA are fabricated in CMOS technology, and their RF characteristics and ESD robustness are verified.

On-Chip Gate Electrostatic Discharge Protection Design for 900 V Power Metal Oxide Semiconductor Field Effect Transistor Using Punch-Through Diode Without Degrading Switching Loss.

In order to protect the gate oxide from electrostatic discharge (ESD) in power MOSFET, the on-chip ESD protection circuits are required. Zener diode on poly silicon gate was normally used in power device because Zener diode structure was easy to merge with conditions of vertical structure without adding electrode. However, merged Zener diode can make unnecessary gate capacitance, and then switching characteristics are degraded by added capacitance. In this paper, a stacked punch-through diode (PT diode) with lower capacitance than Zener diode was designed for 900 V power MOSFET. The PT diode was consisted on doped polysilicon gate between the gate pad and the source pad. The electrical characteristics of this device was designed and analyzed by TCAD simulation and experiments. On the basis of this analysis, the stacked PT diode for ESD protection was optimized and compared with conventional Zener diode.