Design Of Electronic System Research Articles

Brain-inspired methods for achieving robust computation in heterogeneous mixed-signal neuromorphic processing systems

Abstract Neuromorphic processing systems implementing spiking neural networks with mixed signal analog/digital electronic circuits and/or memristive devices represent a promising technology for edge computing applications that require low power, low latency, and that cannot connect to the cloud for off-line processing, either due to lack of connectivity or for privacy concerns. However, these circuits are typically noisy and imprecise, because they are affected by device-to-device variability, and operate with extremely small currents. So achieving reliable computation and high accuracy following this approach is still an open challenge that has hampered progress on the one hand and limited widespread adoption of this technology on the other. By construction, these hardware processing systems have many constraints that are biologically plausible, such as heterogeneity and non-negativity of parameters. More and more evidence is showing that applying such constraints to artificial neural networks, including those used in artificial intelligence, promotes robustness in learning and improves their reliability. Here we delve even more into neuroscience and present network-level brain-inspired strategies that further improve reliability and robustness in these neuromorphic systems: we quantify, with chip measurements, to what extent population averaging is effective in reducing variability in neural responses, we demonstrate experimentally how the neural coding strategies of cortical models allow silicon neurons to produce reliable signal representations, and show how to robustly implement essential computational primitives, such as selective amplification, signal restoration, working memory, and relational networks, exploiting such strategies. We argue that these strategies can be instrumental for guiding the design of robust and reliable ultra-low power electronic neural processing systems implemented using noisy and imprecise computing substrates such as subthreshold neuromorphic circuits and emerging memory technologies.

Parametric Study of Cavity IEMP Responses in a Cylinder by Coupling Monte Carlo Method and 3-D Electromagnetic Particle-in-Cell Method

Internal electromagnetic pulse generated inside a cavity, known as Cavity IEMP, would disturb or damage sensitive electronic systems inside a spacecraft when illuminated by transient X-rays. To ensure their normal operations, accurate prediction and analysis of Cavity IEMP responses are required. In this article, the physical phenomena involved in three-dimensional (3-D) Cavity IEMP problems are numerically studied, including the interaction process between X-rays and the cavity wall material and the self-consistent process involving the motion of electrons and the evolution of electromagnetic fields. The interaction process is simulated with the Monte Carlo method to obtain the actual emission characteristics of forward electrons emitted into a cavity, including their yields, energy, and angular spectra, while the self-consistent process is simulated with a proposed 3-D electromagnetic particle-in-cell method to solve electromagnetic fields generated inside a cavity, whose driving forces are forward electrons with the calculated emission characteristics. This method fully considers electrons with different energies and directions and their impacts on the generated electromagnetic fields. With such method, the electromagnetic field distribution inside a cylinder exposed to transient X-rays is discovered based on the actual emission characteristics of X-ray-induced forward electrons. Furthermore, as forward electron emission characteristics are determined by properties of X-rays and cavities, the impacts of the blackbody temperature in X-ray energy spectrum, the cylinder wall thickness, and the cylinder wall material on the intensity of generated electric fields are fully explored. Based on the results, several suggestions are given to protect electronic systems in cavities against the electromagnetic coupling from Cavity IEMP. The study would guide radiation hardening design of electronic systems in spacecraft.

Optimization design of electronic commerce system based on the basic principles of software engineering

Based on the basic principles of software engineering, this paper optimizes the design of e-commerce system from the aspects of demand analysis, system design, coding, implementation, testing and maintenance. Specifically, this paper adopts the object-oriented software development method, using the UML modeling tools to model the system, adopted the MVC architecture mode to realize the stratification of the system, using the front-end technology such as HTML, CSS, JavaScript to realize the user interface design of the system, combined with the back-end technology such as Java, JSP, the Servlet system. Through the system test and the use of code quality control tools, the system is accepted, and the maintenance of the system is planned and designed. Finally, this paper realizes an easy-to-use, stable, safe and efficient e-commerce system.

Design, fabrication and assembly considerations for electronic systems made of fibre devices

Design, fabrication and assembly considerations for electronic systems made of fibre devices

Analysis of Redundancy Techniques for Electronics Design—Case Study of Digital Image Processing

Electronic circuits/systems operating in harsh environments such as space are likely to experience faults or failures due to the impact of high-energy radiation. Given this, to overcome any faults or failures, redundancy is usually employed as a hardening-by-design approach. Moreover, low power and a small silicon footprint are also important considerations for space electronics since these translate into better energy efficiency, less system weight, and less cost. Therefore, the fault-tolerant design of electronic circuits and systems should go hand in hand with the optimization of design metrics, especially for resource-constrained electronics such as those used in space systems. A single circuit or system (also called a simplex implementation) is not fault-tolerant as it may become a single point of failure and is not used for a space application. As an alternative, a triple modular redundancy (TMR) implementation, which uses three identical copies of a circuit or system and a voter to perform majority voting of the circuits and systems outputs, may be used. However, in comparison with a simplex implementation, a TMR implementation consumes about 200% more area and dissipates 200% more power when circuits or systems are triplicated. To mitigate the area and power overheads of a TMR implementation compared to a simplex implementation, researchers have suggested alternative redundancy approaches such as selective TMR (STMR) insertion, partially approximate TMR (PATMR), fully approximate TMR (FATMR), and majority voting-based reduced precision redundancy (VRPR). Among these, VRPR appears to be promising, especially for inherently error-tolerant applications such as digital image/video/audio processing, which is relevant to space systems. However, the alternative redundancy approaches mentioned are unlikely to be suitable for the implementation of control logic. In this work, we analyze various redundancy approaches and evaluate the performance of TMR and VRPR for a digital image processing application. We provide MATLAB-based image processing results corresponding to TMR and VRPR and physical implementation results of functional units based on TMR and VRPR using a 28-nm CMOS technology.

Design Analysis of Prosthetic Unilateral Transtibial Lower Limb with Gait Coordination

People with lower limb amputations struggle through difficulties during locomotion in their daily activities. People with transtibial amputations take support from prosthetic legs for systematic movement. During motion, they experience some mobility issues while using general prosthetic limbs regarding gait pattern. The design of a prosthetic-controlled lower limb with gait synchronization for physically disabled persons is the main goal of the present research work, which can provide an improved walking experience. The design and performance analysis of prosthetic lower limbs for people with transtibial amputations is performed in the present paper. The designed rehabilitation system shows synchronization between the normal and the prosthetic limbs achieved with gait coordination. The dynamics of the lower extremities in different postural activities are used for design purpose utilizing Euler–Lagrange motion theory. The artificial motion of the knee and the ankle joints function through the angular movement of the servo motors according to the movements of the rotary encoders placed on the sound limb joints. The range of motion of both the sound and prosthetic limbs are compared for different steps during a gait cycle. The prosthetic electronic system design of the artificial lower limb is able to show the gait style of human being with body kinesics. The nonlinear domain stability analysis of the designed prosthetic limb is presented through the Lyapunov method. A PIDF2 controller tuning process is implemented for the designed limb’s performance improvement. The designed prosthetic system is beneficial for people with unilateral transtibial amputations with a great societal impact.

Virtual Reality-Based Design and Performance Simulation of Electronic and Communication Systems

Virtual Reality-Based Design and Performance Simulation of Electronic and Communication Systems

Interview With Prof. Sung-Mo (Steve) Kang

Nicola Nicolici: Good afternoon. Let me welcome Prof. Kang from the University of California at Santa Cruz (UC Santa Cruz). Prof. Kang is an electrical engineer, scientist, professor, author, inventor, and entrepreneur. Currently, he is a distinguished professor emeritus at UC Santa Cruz. He has contributed extensively to the fields of computer-aided design for electronic circuits and systems. He holds 15 U.S. patents, has published over 500 articles, and has won numerous awards for his achievements. He has led the development of the world’s first 32-bit microprocessor chip, Bellmac-32, as a technical supervisor at ATT Bell Labs, Murray Hill, NJ, USA, and has designed satellite-based private communication networks as a member of technical staff.

Dynamic IGBT Three-Dimensional Thermal Network Model Considering Base Solder Degradation and Thermal Coupling Between IGBT Chips

With the development of power electronic technology, the thermal characteristics of high-power insulated gate bipolar transistor (IGBT) module are vital information for thermal management of power electronic equipment, reliability analysis, and thermal design of power electronic system. However, the present commonly used lumped thermal network model based on thermal resistance and heat capacity still has some limitations in accurately predicting the junction temperature of IGBT modules, significantly once considering the degradation of base solder in high-power IGBT modules. In this paper, the thermal behavior of high-power IGBT chips under different base solder degradation is studied by the finite element method (FEM). The results show that the degradation of the base solder has effects on the thermal impedance between the junction and the case, which should be fastidiously thought about within the thermal network model modeling. As a result, a dynamic three-dimensional thermal network model that takes into account the thermal interaction between IGBT chips, as well as the degradation of the base solder, is proposed in this paper. The proposed thermal network model can estimate the junction temperature of a high-power IGBT module correctly and fast based on the real degradation of the base solder. Finally, finite element simulation and experimental findings are used to validate the proposed dynamic three-dimensional thermal network model. The results show that the dynamic three-dimensional thermal network model has comparable accuracy to finite element simulation and test results. At the same time, the dynamic three-dimensional thermal network model responds faster than the finite element simulation.

Squeeze-Printing Ultrathin 2D Gallium Oxide out of Liquid Metal for Forming-Free Neuromorphic Memristors.

Two-dimensional (2D) metal oxides exhibit extraordinary mechanical and electronic properties, leading to new paradigms in the design of electronic and optical systems. However, as a representative, a 2D Ga2O3-based memristor has rarely been touched, which is hindered by challenges associated with large-scale material synthesis. In this work, the ultrathin 2D Ga2O3 layer (∼3 nm thick) formation on the liquid gallium (Ga) surface is transferred with lateral dimensions over several centimeters on a substrate via the squeeze-printing strategy. 2D Ga2O3-based memristors exhibit forming-free and bipolar switching behaviors, which also reveal essential functions of biological synapse, including paired-pulse facilitation, spiking timing-dependent plasticity, and long-term depression and potentiation. These results demonstrate the potential of 2D Ga2O3 material for neuromorphic computing and open up an avenue for future electronics application, such as deep UV photodetectors, multimode nanoresonators, and power switching devices.

Approaches for Working with the Body in the Design of Electronic Music Performance Systems

ABSTRACT This article outlines a body-centred focus in the design of performance systems for electronic music. Through a movement-led design process, I discuss the interaction of the body, controllers, data and mapping. A flat hierarchy approach to performance system design aims to support bodily autonomy in performance, challenge human-machine dualism and expand the definition of virtuosity in performance to include system virtuosity. The affordances and behaviours of the components of performance systems are discussed in terms of their cooperation. With an awareness of the non-neutrality of data, controllers, and sensors, I outline methods for making adaptive and flexible systems which respond to and respect individual bodies. This embodied and hybrid approach to system design can facilitate posthuman expression in electronic music performance.

Transmission line characterization and modeling for electronic circuits and systems design

Channel bandwidth-limited high-speed links or interfaces make circuit solutions not efficient. Both recent and subsequent links (SerDes-Serializer/Deserializer) design demand efficient and effective coupling between future circuit design, communication, and optimization. The challenges vary and new solutions are needed. In this article, an analytical wireline model is presented to predict electronic path loss towards adequate designs of electronic circuits and systems. An open loop system analysis is adapted in this paper. Our model was tested against different channels: a legacy channel with via stub discontinuity and FR4 dielectric, and a more recent microwave-engineered channel without stub and NELCO 6,000 dielectric, a very good matching attained. Good agreement was observed between our model and electromagnetic full-wave simulation data, as a result showed high level of applicability to thin-film microstrip line for adequate circuit design. The model is recommended for electronic engineers for adequate and faster interfaces and high-speed links designs.

The New Small Wheel electronics

The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that don't originate from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the “small” Thin Gap Chambers, with a total of 2.45 million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm2 at the expected HL-LHC luminosity of ℒ = 7.5 × 1034 cm-2 s-1. The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.

Teaching undergraduate students to think like real‐world systems engineers: A technology‐based hybrid learning approach

AbstractA hybrid teaching approach that relied on combining Project Based Learning with Team Based Learning was developed in an engineering module during the past 5 years. Our motivation was to expose students to real‐world authentic engineering problems and to steer them away from the classical banking approach, with a view to developing their systems engineering skills via collaborative learning. Our third year module was called Team Design and Project Skills and was concerned with 320 students dividing themselves in teams to develop a smart electronics system. We reveal module design details and discuss the effectiveness of our teaching approach via analysis of student grades during the past 5 years, as well as data from surveys that were completed by 68 students. 64% of surveyed students agreed that the module helped broaden their perspective in electronic systems design. Moreover, 84% recognized that this module was a valuable component in their degree programme. Adopting this approach in an engineering curriculum enabled students to integrate knowledge in areas that included control systems, image processing, embedded systems, sensors, as well as team working, decision making, trouble shooting and project planning.

Design of the readout electronics system with high event rate based on the Micromegas Detector

This paper presents a multi-channel readout electronic system with a high event rate. Its primary purpose is to meet the increasing collision luminosity in large particle physics collision experiments in recent years, thus bringing about the requirement of high event rates for readout electronics systems. This system is designed for Micromegas detectors and consists of front-end readout boards (FEB) and a data acquisition board (DAQ). It realizes that at 128 channels simultaneous readout, each channel can work at the maximum 2.2 Mhits/s event rate. Each event data contains amplitude and time information, which is read out by FEB. The event data will be sent to DAQ by the GTX transceiver at 3.2 Gbps and then transferred to the data acquisition software. In the data acquisition software, each particle hit position and track will be analyzed and reconstructed. The specific characteristics and implementations of this readout electronic system are described in detail.

An Overview of Complex Instability Behaviors Induced by Nonlinearity of Power Electronic Systems with Memristive Load

The proposal of the memristor, considered as the fourth basic circuit element, suggests a new possibility for the design of high-performance power electronic systems. However, it also brings new challenges. At present, more and more electrical equipment and systems have demonstrated that their external characteristics can exhibit “8”-shaped hysteresis loops and can be regard as memristive equipment and systems. In order to satisfy the requirements of controllability, flexibility, efficiently, and so on, most memristive equipment and systems are not directly connected to the power grid but instead obtain their own required powering through various forms of power electronic converters. Note that memristive loads are distinctive and demonstrate unique nonlinear behaviors. Similarly, there can be nonlinearity from the resistor (R), inductor (L), or capacitor (C) load, but there is no combination of only R, L, and C that could produce memristive characteristics. In particular, the memristance of memristive devices changes continuously during the operation process; in addition, practical power electronic systems composed of memristive devices and power supplies have strong nonlinear characteristics, which are more likely to result in various complex behaviors and are not conducive to the stable operation of the systems. Therefore, exploring complex instability behaviors of power electronic systems with strong nonlinearity in depth is necessary for better protection and utilization of memristive devices. This paper provides an outline of the status of research on complex behaviors of power electronic systems with memristive load; it is expected to provide guidance for the study of complex behavior of strongly nonlinear systems.

Real-Time FPGA Simulation of High-Voltage Silicon Carbide MOSFETs

This article presents a real-time field-programmable gate array (FPGA)-based dynamic model of high-voltage and high-current silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> ) half-bridge power modules. The dynamic switching model utilizes the Shichman and Hodges equations using voltage-dependent nonlinear device capacitances and module electrical parameters to obtain an accurate dynamic model of the device switching transients. The key device states gate-source voltage, drain current, and drain-source voltage are modeled and discretized using forward Euler discrete integration method. Analysis of synthesizing the discrete-time model into real-time FPGA-based system with real-time data output from the on-board digital-to-analog converter is presented in detail. The model is utilized in modeling a 320-kW, medium-voltage dc/dc dual-active bridge converter and verified using dynamic experimental results from a 3.3-kV SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> half-bridge power module. It has been shown that the presented discrete-time dynamic switching model accurately describes the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> switching transients of the SiC power module at various voltage and current levels. Such models are useful for rapid and cost effective design and prototyping of SiC-based power electronic systems by defining key design and operating parameters, such as deadtime, switching frequency, and switching losses.

Design of Plc-based Pipe Pile Residual Slurry Recovery Equipment Control System

To solve the cost loss caused by the low recovery efficiency of pipe pile residual slurry, as well as the pollution of the environment during discharge, a control system of pipe pile residual slurry recovery equipment is designed. The equipment is controlled by PLC (Programmable Logic Controller), aiming at the problem that the traditional PID (Proportion Integration Differentiation) cannot modify the parameters in real time to meet the accuracy requirements of the residual slurry density. The fuzzy PID controller algorithm is proposed, and the simulation analysis is carried out by MATLAB at the same time. Through PLC selection, PLC I/O allocation, electronic control system design, program writing, and HMI (Human Machine Interface) establishment, the information interaction is achieved between equipment and people while monitoring the production process. Through on-site production tests, the equipment is proved to be reliable and efficient, which can make the residual slurry recovery utilization rate reach more than 90%, and reduce the production cost of pipe piles.

Design of novel high speed parallel prefix adder

Adders are crucial logical building blocks found almost in all the modern electronic system designs. In the adder architecture design, the fundamental issue is the propagation latency in the carry chain. As the length of the input operands increases, the length of the carry chain along with it. Parallel prefix adders, which address the problem of carry propagation in adders, are the most efficient adder topologies for hardware implementation. However, delay reduction still could be achieved for very high speed applications. Hence, in this paper design of 16bit novel parallel prefix adder is proposed and compared against the existing parallel prefix adder architectures. The design and simulation are carried out using xilinx vivado for field- programmable gate array (FPGA) simulation and Cadence® for ASIC. The results of ASIC implementation demonstrate 17.8% delay reduction while compared to sparse kogge-stone adder.

SHDL—A Hardware Description Language and Open-Source Web Tool for Online Digital Systems Design Teaching

Hardware description languages and tools require a considerable amount of teaching activities in a digital systems design course, which is difficult to accommodate in a limited time frame, and to use for e-learning. This paper presents our user-friendly and open-source web-based digital design tool, SHDL, which is used to describe and simulate hardware components and translate them into a standard language. SHDL is a teaching language and tool for digital design, which aims to improve the teaching and learning experience in digital systems design courses. The use and evaluation of the proposed online teaching model for the Digital Electronic Systems Design (DESD) course, using the SHDL tool for e-learning during the COVID-19 phase, is presented. Using the SHDL language and web tool, we have created many examples of digital circuits that prepare students to explore their own designs. The example components can also be used as digital system modules, leading to better modularity of the final project. The use of SHDL in the DESD course has shown that the proposed language leads to fewer syntax, simulation and synthesis errors in the designed circuits. The evaluation results show that at the end of the laboratory exercises, there was no longer a difference in knowledge between the students without prior VHDL experience and the other students. The results encourage us to continue using SHDL, and to complement the traditional DESD teaching methods with e-learning.