Design of novel high speed parallel prefix adder

Abstract

Adders are crucial logical building blocks found almost in all the modern electronic system designs. In the adder architecture design, the fundamental issue is the propagation latency in the carry chain. As the length of the input operands increases, the length of the carry chain along with it. Parallel prefix adders, which address the problem of carry propagation in adders, are the most efficient adder topologies for hardware implementation. However, delay reduction still could be achieved for very high speed applications. Hence, in this paper design of 16bit novel parallel prefix adder is proposed and compared against the existing parallel prefix adder architectures. The design and simulation are carried out using xilinx vivado for field- programmable gate array (FPGA) simulation and Cadence® for ASIC. The results of ASIC implementation demonstrate 17.8% delay reduction while compared to sparse kogge-stone adder.