Area & power modeling for different tree topologies of parallel prefix adders

Abstract

Parallel prefix adder (PPA) being an indispensable component of processors needs prompt estimation of design metrics at the initial stage of design cycle. However, the available commercial tools take significant amount of time for the estimation process. The prior availability of area and power models can greatly reduce time-to-market. Symmetrical construction and quick computational ability of PPAs make them competent candidates for adder circuits in complex applications. This paper proposes area and power models for Field Programmable Gate Arrays (FPGA) implementation of classic PPAs, targeted to Xilinx Zynq-7000 family. The available literature barely presents parameters estimation and their analysis for PPAs. Therefore, modeling proposed in this paper is a novel work. PPA structures are simulated, synthesized and implemented using commercial tool i.e. VIVADO IDE. Models have been developed using curve fitting and validated against commercial tool. Results show an average estimation error ranging from 0.37% to 1.34% in case of area modeling and 0.23% to 0.59% in case of power modeling which are comparable with state of the art.