Abstract
Channel bandwidth-limited high-speed links or interfaces make circuit solutions not efficient. Both recent and subsequent links (SerDes-Serializer/Deserializer) design demand efficient and effective coupling between future circuit design, communication, and optimization. The challenges vary and new solutions are needed. In this article, an analytical wireline model is presented to predict electronic path loss towards adequate designs of electronic circuits and systems. An open loop system analysis is adapted in this paper. Our model was tested against different channels: a legacy channel with via stub discontinuity and FR4 dielectric, and a more recent microwave-engineered channel without stub and NELCO 6,000 dielectric, a very good matching attained. Good agreement was observed between our model and electromagnetic full-wave simulation data, as a result showed high level of applicability to thin-film microstrip line for adequate circuit design. The model is recommended for electronic engineers for adequate and faster interfaces and high-speed links designs.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: Indonesian Journal of Electrical Engineering and Computer Science
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
