Electric Field In Gate Oxide Research Articles

Performance enhancement of 4H-SiC superjunction trench MOSFET with extended high-K dielectric

This paper proposes a 4H-SiC superjunction trench MOSFET with extended high-K dielectric under metal gate (EHK SJ-TMOS). The characteristics of EHK SJ-TMOS include the use of the high-K (HK) dielectric as the gate dielectric and the extension of the HK dielectric as a deep trench into the N-type drift region. The extended HK trench effectively modulates the electric field distribution in the SJ drift region, which improves the breakdown voltage (BV). The introduction of HK dielectric also assists in depleting the SJ drift region, which enables the drift region of EHK SJ-TMOS to use a higher doping concentration, thereby reducing Ron,sp. Furthermore, the application of high-K gate dielectric alleviates the high gate oxide electric field problem in conventional SiC superjunction trench MOSFETs (SiC SJ-TMOS). The simulation results demonstrate that EHK SJ-TMOS exhibits a 59.2 % reduction in Ron,sp, a 2.4 % increase in BV, and a 156.5 % improvement in the FOM (FOM = BV2/Ron,sp) compared to the SiC SJ-TMOS, indicating enhanced performance.

A 4H-SiC p-channel insulated gate bipolar transistor with higher breakdown voltage and superior V F·C res figure of merit

A silicon carbide p-channel insulated gate bipolar transistor (IGBT) with higher breakdown voltage (BV) and low V F·C res figure of merit (FOM) has been simulated, fabricated, and characterized successfully. The proposed IGBT adds two n-type implant regions in the junction FET (JFET) area and increases the gate oxide thickness above the JFET area to reduce the reverse transfer capacitance (C res) and gate oxide electric field (E ox). The proposed structure notably lowers E ox below 3 MV cm−1 while elevating the BV to 16.6 kV. A new FOM of V F·C res is defined to evaluate the trade-off between the on-state and the C res characteristics. The experimental results demonstrate that a lower V F·C res FOM of 0.369 V·pF is achieved from the proposed IGBT with a reduction of 66.4%, compared to the conventional current spreading layer IGBT. Meanwhile, the simulated turn-on and turn-off times of the proposed IGBT are reduced by 29.4% and 20%, respectively.

A SiC asymmetric cell trench MOSFET with a split gate and integrated p+-poly Si/SiC heterojunction freewheeling diode

A new SiC asymmetric cell trench metal–oxide–semiconductor field effect transistor (MOSFET) with a split gate (SG) and integrated p+-poly Si/SiC heterojunction freewheeling diode (SGHJD-TMOS) is investigated in this article. The SG structure of the SGHJD-TMOS structure can effectively reduce the gate-drain capacitance and reduce the high gate-oxide electric field. The integrated p+-poly Si/SiC heterojunction freewheeling diode substantially improves body diode characteristics and reduces switching losses without degrading the static characteristics of the device. Numerical analysis results show that, compared with the conventional asymmetric cell trench MOSFET (CA-TMOS), the high-frequency figure of merit (HF-FOM, R on,sp × Q gd,sp) is reduced by 92.5%, and the gate-oxide electric field is reduced by 75%. In addition, the forward conduction voltage drop (V F) and gate-drain charge (Q gd) are reduced from 2.90 V and 63.5 μC/cm2 in the CA-TMOS to 1.80 V and 26.1 μC/cm2 in the SGHJD-TMOS, respectively. Compared with the CA-TMOS, the turn-on loss (E on) and turn-off loss (E off) of the SGHJD-TMOS are reduced by 21.1% and 12.2%, respectively.

Cell Design Consideration in SiC Planar IGBT and Proposal of New SiC IGBT With Improved Performance Trade-Off

In silicon carbide (SiC) planar insulated-gate bipolar transistor (IGBT), a large distance between neighboring p-bodies is beneficial to enhance the on-state conductivity modulation, but will expose the gate oxide to high electric field in off-state. With p-bodies placed closer, the gate oxide field is reduced, but the conductivity modulation is suppressed. In this work, a new SiC planar IGBT with oxide shield is proposed and studied by TCAD simulations. The proposed SiC IGBT achieves improved trade-off between on-state voltage drop (VON) and maximum gate oxide electric field (Eox-m). When a quite larger distance between neighboring p-bodies is adopted in the proposed SiC IGBT, a low VON is obtained, while the Eox-m can be kept at a small value with the oxide shielding structures protecting the gate oxide. Switching characteristics are also studied, and the proposed SiC-IGBT delivers much better trade-off between turn-off energy loss (EOFF) and VON than the conventional SiC planar IGBT.

A novel SiC superjunction MOSFET with three-level buffer and unipolar channel diode

A novel SiC trench superjunction MOSFET with an integrated unipolar channel diode and three-level buffer (DioSJ-MOS) is proposed, which features an additional planar channel and a three-level buffer (TLB). The planar channel brings the effect of dual-channel forward conduction and unipolar reverse conduction, reducing specific on-resistance and improving third quadrant performance. The TLB composed of P-pillar, P + body and thickened oxide layer optimizes the in-body and gate-oxide electric field, improving gate oxide reliability, enhancing device breakdown voltage and lessening the gate-drain coupling. Furthermore, an embedded channel diode with low potential barrier for electrons transport replaces internal parasitic diode successfully. Compared with conventional MOSFET (SF-MOS) and trench/planar MOSFET (TP-MOS), DioSJ-MOS exhibits a lower specific on-resistance (1.08 mΩ cm2), an improved gate oxide electric field (2.6 MV/cm) and a better third quadrant performance （1.56 V） due to TLB structure and unipolar channel diode. Meanwhile, the gate to drain charge (QGD) and capacitance (CGD) of DioSJ-MOS are significantly reduced by about 3 × and 4 × in comparison with TP-MOSFET. Therefore, the overall enhanced performance indicates that DioSJ-MOS is more attractive device in high-voltage, high-reliability and high-frequency applications.

Performance Enhancement of 2.3 kV 4H-SiC Planar-Gate MOSFETs Using Reduced Gate Oxide Thickness

Planar-gate 2.3 kV 4H-SiC power MOSFETs were successfully fabricated in a commercial foundry with the gate oxide thickness reduced from 55 to 27 nm for the first time. Results of numerical simulations demonstrate acceptable gate oxide electric field despite the increased blocking voltage. For a gate bias of 15 V, the measured specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {ON},\text {sp}}$ </tex-math></inline-formula> ) and high-frequency figures-of-merit (FOM[ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {ON}} \times {C}_{\text {gd}}$ </tex-math></inline-formula> ], FOM[ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {ON}} \times {Q}_{\text {gd}}$ </tex-math></inline-formula> ]) were improved by a factor of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.3\times $ </tex-math></inline-formula> by reducing the gate oxide thickness even at the larger blocking voltage. Analytical modeling shows that the channel and accumulation layer resistances are still important contributors even at this larger blocking voltage capability. Operating the 27 nm gate oxide devices with the commonly accepted ON-state gate oxide electric field of 4 MV/cm for reliable operation makes the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {ON},\text {sp}}$ </tex-math></inline-formula> and FOMs for the 27 nm gate oxide case 10% worse than the 55 nm gate oxide case. However, the reduced gate bias of 11 V for the 27 nm gate oxide case reduces input switching power loss in half from a gate drive perspective. In addition, operation at this gate bias makes the saturation current for the 27 nm gate oxide devices three times smaller than for the conventional devices operating at a gate bias of 20 V, which will proportionally increase short-circuit withstand time.

A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance

A split gate MOSFET (SG-MOSFET) is widely known for reducing the reverse transfer capacitance (C RSS). In a 3.3 kV class, the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field. In addition to the poor static performance, the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering (DIBL) caused by the high gate oxide electric field. As such, a 3.3 kV 4H-SiC split gate MOSFET with a grounded central implant region (SG-CIMOSFET) is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance. The SG-CIMOSFET has a significantly low on-resistance (R ON) and maximum gate oxide field (E OX) due to the central implant region. A grounded central implant region significantly reduces the C RSS and gate drain charge (Q GD) by partially screening the gate-to-drain capacitive coupling. Compared to a planar MOSFET, the SG MOSFET, central implant MOSFET (CIMOSFET), the SG-CIMOSFET improve the R ON×Q GD by 83.7%, 72.4% and 44.5%, respectively. The results show that the device features not only the smallest switching energy loss but also the fastest switching time.

3.3-kV 4H-SiC Split-Gate DMOSFET with Floating p+ Polysilicon for High-Frequency Applications

A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (CGD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction field effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and specific on resistance (RON,SP) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (CGD) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency figure of merit (HF-FOM = RON,SP × CGD) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an EMOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications.

Design and Fabrication of 4H-Sic Mosfets with Optimized JFET and p-Body Design

In this paper, 4H-SiC planar MOSFETs were designed and fabricated. By using TCAD tool, the trade-off between on-resistance and maximum gate oxide electric field was optimized. With optimized gate oxide growth process, the gate oxide’s critical electric field of 9.8 MV/cm and the effective barrier height of 2.57 eV between SiO2 and 4H-SiC were obtained. The field effective mobility with different p-body doping was compared and studied. The MOS interface state density of 1.12E12 cm-2eV-1 at EC - EIT = 0.21 eV and channel mobility of 19.3 cm2/Vs at VGS = 20 V were obtained. The fabricated MOSFET’s on-resistance of 6.4 mΩcm2 was obtained with hexagonal cell structure which is very consistent with the simulation results.

A trench/planar SiC MOSFET integrated with SBD (TPSBD) for low reverse recovery charge and low switching loss

In this paper, with Sentaurus TCAD simulation, the trench/planar MOSFET (TPMOS) shows a much lower electric field in gate oxide and a smaller gate charge than the traditional trench MOSFET (TMOS) and commercial double trench MOSFET (DTMOS). Besides, compared with DTMOS, the TPMOS also has a smaller specific on-resistance. These advantages make the TPMOS more suitable for being integrated with a Schottky barrier diode (SBD) to reduce both conduction loss and switching loss. Therefore, the trench/planar 4 H-SiC MOSFET integrated with SBD (TPSBD) is firstly proposed and studied. For the TPSBD, the static simulation results show that the maximum reverse current without the body diode turning on is 1320 A cm−2 in the third quadrant. In the double pulse test with a load current of 1000 A cm−2, the body diode of the TPSBD is successfully suppressed. However, the body diodes of the other three MOSFETs turn on and contribute 75% of the freewheeling currents, even though an external SBD is anti-parallel with these MOSFETs. The body diodes still contribute 25% of the freewheeling currents, even though the active area of the anti-parallel SBD increases three times. Compared with TMOS, DTMOS and TPMOS, the reverse recovery charge of the TPSBD reduces by 91%, 88% and 96%, respectively. The total switching loss of the TPSBD also reduces by 83%, 71% and 66% in contrast with TMOS, DTMOS and TPMOS, respectively. Therefore, the TPSBD is a superior choice for low reverse recovery charge and low switching loss application.

Analysis of the Negative-Bias-Temperature-Instability on Omega-Gate Silicon Nanowire SOI MOSFETs with Different Dimensions

This work presents an experimental andThis work presents an experimental and simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation. simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation.

Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation

Gate oxide reliability of a trench-gate SiC MOSFET can be improved by incorporating a gate protection structure, but the resulting parasitic JFET resistance is one major drawback. For reduction of on-resistance, a new method of localized high-concentration n-type doping in JFET regions (JD) is developed. Utilizing process and device simulation by TCAD, the optimal condition of JD that enables maximum device performance is derived. By fabricating a device with the optimal JD structure, the on-resistance is successfully reduced by 25% compared to a conventional device without JD, while maintaining the withstand voltage and the gate oxide electric field at the same level. As a result, a device exhibiting a specific on-resistance of 1.84 mΩcm2 and a breakdown voltage of 1560 V is obtained. The optimal JD structure maintains the short-circuit safe operation area comparable to that for the structure without JD. Thus, by reducing the JFET resistance while minimizing effects on other characteristics, localized JD is shown to be an effective means of realizing a reliable, low-resistance SiC power device.

A novel 4H-SiC MOSFET for low switching loss and high-reliability applications

A novel 1200 V 4H-SiC MOSFET, which features a current spreading layer, a split-gate and a central P+ implant in the junction field effect transistor region (CSI-MOSFET), is proposed. The CSI-MOSFET achieves a better trade-off among specific on-resistance, maximum electric field in gate oxide and switching loss. The CSI-MOSFET is comprehensively optimized with numerical simulation, and then two kinds of CSI-MOSFETs (FCSI-MOSFET and GCSI-MOSFET with a floating/grounded central P+ implant) are further investigated. Compared with the conventional double implanted MOSFET (VDMOSFET), both FCSI-MOSFET and GCSI-MOSFET demonstrate a smaller on-resistance, and a smaller gate charge. Moreover, a maximum electric field in the gate oxide of 0.92 MV cm−1 is realized in GCSI-MOSFET, without breakdown voltage degradation. To our best knowledge, it is the lowest electric field among those reported on 1200 V SiC MOSFETs. For dynamic characteristics, the FCSI-MOSFET has the largest switching loss and the largest on-state voltage drop, due to the negative charges stored in the floating P+ implant region. On the contrary, the GCSI-MOSFET achieves the same low switching loss as that of the split-gate MOSFET with an extreme short gate length (0.2 μm), because there is no charge in the grounded P+ implant region. Therefore, the GCSI-MOSFET is far superior for low switching loss and high-reliability applications.

Comparative Study of SiC Planar MOSFETs With Different p-Body Designs

Silicon carbide MOSFET has been commercialized for many years. Its performance is still improving especially for high-frequency application. High-frequency figure-of-merit (HF-FOM) ${R}{ \mathrm{\scriptstyle ON}}^\ast {C}_{\text {GD}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}{}^\ast ~{Q}_{\text {GD}}$ were used for a comprehensive evaluation of the performance of MOSFET. In this article, SiC planar MOSFETs with different p-body designs were comparatively studied. A new planar MOSFET with buffered gate and thick central oxide gate structure (TCOX-MOS) was proposed to further improve the gate oxide electric field in OFF-state and HF-FOM. Compare to the conventional planar MOSFET (C-MOS), the maximum gate oxide electric field, gate–drain charge, and HF-FOM ( ${R}_{ \mathrm{\scriptscriptstyle ON}} {}^{\ast } {Q}_{\text {GD}}$ ) of TCOX-MOS are 32%, 83%, and 84% lower, respectively. Furthermore, TCOX-MOS shows less short-channel effects by better channel shielding structure. The results show that TCOX-MOS is a more attractive device structure.

Different JFET Designs on Conduction and Short-Circuit Capability for 3.3 kV Planar-Gate Silicon Carbide MOSFETs

Both large current capability and strong short-circuit (SC) ruggedness are necessary for 3.3 kV SiC MOSFETs to improve system efficiency and reduce costs in industrial and traction applications. In this paper, the effects of Junction Field Effect Transistor (JFET) region width and JFET doping (JD) on conduction and SC capability of the 3.3 kV planar-gate SiC MOSFETs are systematically investigated by experiments and simulations. When the JFET width (WJFET) of device without JD is smaller, the positive temperature coefficient of the special on-resistance (Ron,SP) is larger. The JD is effective to improve the Ron,SP, but excessive electric field in gate oxide induced by JD should be paid more attention. The optimization of WJFET can be used to improve both Ron,SP and short circuit withstanding time (SCWT) at the same time. The drain-source current (Ids) and SCWT of the optimized devices are 50 A and more than $20~{\mu }\text{s}$ , respectively, which is state-of-the-art for 3.3 kV SiC MOSFETs.

Study of Asymmetric Cell Structure Tilt Implanted 4H-SiC Trench MOSFET

The reliability of gate dielectrics is one of the key issues in SiC Trench MOSFET. While reducing the gate oxide electric field in OFF state through dedicated shielding structures by various designs, JFET resistances are often introduced. In this letter, a new asymmetric cell structure, tilt implanted 4H-SiC trench MOSFET (ACTI-TMOS) is proposed. This approach achieves a better trade-off between gate oxide electric field and specific ON-resistance ( $R_{ \mathrm{\scriptscriptstyle ON}}$ ). The 2D numerical simulation was used to compare ACTI-TMOS with double trench MOSFET and gate bottom p-well trench MOSFET. The maximum gate oxide electric field of the ACTI-TMOS is 42.1% and 6.5% lower in OFF state compared to the other two designs. Both gate charge ( $Q_{G}$ ) and gate drain charge ( $Q_{GD}$ ) are significantly improved. The results show that ACTI-TMOS is a more attractive device structure.

Design and simulation on improving the reliability of gate oxide in SiC CDMOSFET

For silicon carbide (SiC) power MOSFETs, gate oxide reliability under high electric stress leading to device failure has become one of the major concerns in actual applications. In this paper, a novel SiC MOSFET with center dielectric layer (CDMOSFET) is proposed to improve the gate oxide robustness. Comparisons of the electric field in gate oxide layer and dielectric layer between CDMOSFETs and conventional SiC MOSFETs have been carried out through the TCAD Silvaco. Numerical simulation results indicate that the peak electric field in gate oxide decreases ~30% (1.1 MV/cm) compared with conventional SiC MOSFETs at breakdown of 2.9 kV. Furthermore, the influence of dielectric layer configuration, including width, thickness and depth, on the reliability of the gate oxide layer is further discussed in detail. The results illustrate that the peak electric field in gate oxide layer is reduced via employing the dielectric layers in the JFET region of MOSFETs owing to the decrease of impact ionization generation rate and perpendicular electrical field along the SiC/SiO2 interface, thus improving the reliability of the gate oxide of SiC MOSFETs.

SiC Trench MOSFET With Shielded Fin-Shaped Gate to Reduce Oxide Field and Switching Loss

A silicon carbide shielded fin-shaped gate metal-oxide-semiconductor field effect transistor (SF-MOS) is proposed in this letter, which utilizes a well-grounded p-region to shield the fin-shaped trench gate. Numerical simulations by Sentaurus TCAD are carried out to study the performance of SF-MOS, and comparisons with conventional trench MOSFET and the state-of-the-art double-trench MOSFET are presented. The maximum electric field in gate oxide of the SF-MOS is effectively lowered to below 3 MV/cm, which is a widely accepted criterion for long-term gate oxide reliability. Furthermore, with the shielding effects, the gate-to-drain charge of the SF-MOS is significantly reduced, leading to lower switching loss.

Effect of Grain Orientation on NBTI Variation and Recovery in Emerging Metal-Gate Devices

This letter identifies and investigates the effect of grain orientation (GO) on negative-bias temperature instability (NBTI) characteristics of emerging metal-gate devices. A modified reaction-diffusion model is presented for estimating the effect of GO on NBTI. It is shown that neglecting the GO effect leads to substantial underestimation of the impact of the gate-oxide electric field (EOX) on the threshold voltage degradation (ΔVTH). Moreover, GO results in significant fluctuation in EOX and, hence, fluctuation in NBTI for ultrascaled CMOS devices. In addition, in FinFETs, stand-alone GO-induced gate-oxide electric field not only results in ΔVTH fluctuation but also decelerates the recovery process.

Performance and Reliability of SiC MOSFETs for High-Current Power Modules

We address the two critical challenges that currently limit the applicability of SiC MOSFETs in commercial power conversion systems: high-temperature gate oxide reliability and high total current rating. We demonstrate SiC MOSFETs with predicted gate oxide reliability of &gt;106 hours (100 years) operating at a gate oxide electric field of 4 MV/cm at 250°C. To scale to high total currents, we develop the Power Overlay planar packaging technique to demonstrate SiC MOSFET power modules with total on-resistance as low as 7.5 m. We scale single die SiC MOSFETs to high currents, demonstrating a large area SiC MOSFET (4.5mm x 4.5 mm) with a total on-resistance of 30 m, specific on-resistance of 5 m-cm2 and blocking voltage of 1400V.