Performance Enhancement of 2.3 kV 4H-SiC Planar-Gate MOSFETs Using Reduced Gate Oxide Thickness

Abstract

Planar-gate 2.3 kV 4H-SiC power MOSFETs were successfully fabricated in a commercial foundry with the gate oxide thickness reduced from 55 to 27 nm for the first time. Results of numerical simulations demonstrate acceptable gate oxide electric field despite the increased blocking voltage. For a gate bias of 15 V, the measured specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {ON},\text {sp}}$ </tex-math></inline-formula> ) and high-frequency figures-of-merit (FOM[ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {ON}} \times {C}_{\text {gd}}$ </tex-math></inline-formula> ], FOM[ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {ON}} \times {Q}_{\text {gd}}$ </tex-math></inline-formula> ]) were improved by a factor of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.3\times $ </tex-math></inline-formula> by reducing the gate oxide thickness even at the larger blocking voltage. Analytical modeling shows that the channel and accumulation layer resistances are still important contributors even at this larger blocking voltage capability. Operating the 27 nm gate oxide devices with the commonly accepted ON-state gate oxide electric field of 4 MV/cm for reliable operation makes the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {ON},\text {sp}}$ </tex-math></inline-formula> and FOMs for the 27 nm gate oxide case 10% worse than the 55 nm gate oxide case. However, the reduced gate bias of 11 V for the 27 nm gate oxide case reduces input switching power loss in half from a gate drive perspective. In addition, operation at this gate bias makes the saturation current for the 27 nm gate oxide devices three times smaller than for the conventional devices operating at a gate bias of 20 V, which will proportionally increase short-circuit withstand time.