Design and simulation on improving the reliability of gate oxide in SiC CDMOSFET

Abstract

For silicon carbide (SiC) power MOSFETs, gate oxide reliability under high electric stress leading to device failure has become one of the major concerns in actual applications. In this paper, a novel SiC MOSFET with center dielectric layer (CDMOSFET) is proposed to improve the gate oxide robustness. Comparisons of the electric field in gate oxide layer and dielectric layer between CDMOSFETs and conventional SiC MOSFETs have been carried out through the TCAD Silvaco. Numerical simulation results indicate that the peak electric field in gate oxide decreases ~30% (1.1 MV/cm) compared with conventional SiC MOSFETs at breakdown of 2.9 kV. Furthermore, the influence of dielectric layer configuration, including width, thickness and depth, on the reliability of the gate oxide layer is further discussed in detail. The results illustrate that the peak electric field in gate oxide layer is reduced via employing the dielectric layers in the JFET region of MOSFETs owing to the decrease of impact ionization generation rate and perpendicular electrical field along the SiC/SiO2 interface, thus improving the reliability of the gate oxide of SiC MOSFETs.