Effect Of Gate Length Research Articles

Si/Si0.7Ge0.3 A2RAM nanowires fabrication and characterization for 1T-DRAM applications

A2RAM devices are fabricated using an adaptation of Si-nanowire process flow, including a Si-SiGe heterostructure. We present the effects of gate length, film thickness, bridge implantation conditions and the presence of LDD impacts on A2RAM memory performance. Despite the accidentally undoped polysilicon gate, we succeed in demonstrating 1T-DRAM programming and operation.

A High Performance Normally-Off AlGaN/GaN Split-Gate Metal-Insulator-Semiconductor High Electron Mobility Transistor (MIS-HEMT) Using Piezo Neutralization Technique

In this paper, we propose a novel normally-off MIS-HEMT structure, mainly using Split-Gate Technology, Piezo Neutralization Technique (PNT), Field Plate Technology. By analyzing the effects of different Al composition in the PNT layer and buffer layer on devices, the Piezo Neutralization Technique is optimized. The current turn-on/off is controlled by changing gate voltage to regulate the horizontal conduction band between the double gates. The effects of gate length and block barrier size between the double gates on device performance are studied. Through two-dimensional device simulation, the operation principle and internal mechanism are analyzed. An improved device with good performance is presented. The threshold voltage Vth is 4.1 V, the peak transconductance is 0.3 S/mm, the maximum drain current is 1.1 A/mm and the breakdown voltage is 1200 V.

Effects of gate length on GaN HEMT performance at room temperature

We report the electrical characteristics at room temperature of (Al,Ga)N/GaN high-electron-mobility transistors with different gate lengths Lg ranging from 0.15 to 2 μm. Static measurements demonstrate an increase of leakage current, whereas the maximum drain–source current and maximum transconductance decrease with increase of the gate length. In addition, drain current–voltage measurements for gate voltage Vgs = −3 V reveal a kink effect, which is pronounced for Lg = 0.15, 0.25, and 0.5 μm and is absent for Lg = 1 and 2 μm. Furthermore, a self-heating effect on the drain current is observed at Vgs = 0 V for a short gate length. By means of deep level transient spectroscopy, we detected one hole trap H1, which is considered to be the main cause of the observed kink effect. Also, the effect of gate length on the static output characteristics and the deep level transient spectroscopy results for Al0.25Ga0.75N/GaN high-electron-mobility transistors is also discussed.

The gate length effect of high-performance monolayer SiAs2 FETs

The monolayer SiAs2 field-effect transistors (FETs) with gate length (L gate) ranging from 1 to 50 nm were investigated by Silvaco-Atlas simulation in which the main parameters of monolayer SiAs2 were obtained by first-principles calculations. Both the p- and n-FET show extremely high on/off current ratio (1014) and low leakage current (10−18 A μm−1), which are independent of gate length within the 15–50 nm range. And monolayer SiAs2 FETs show practically acceptable values of subthreshold slope and drain-induced barrier lowering when L gate ⩾ 30 nm. On the other hand, the p-and n-FETs show highest transconductance (g m) when L gate is between 25 and 35 nm. Our results suggest that the high performance 35 nm gate length monolayer SiAs2 FETs hold great potential for applications in low-dimensional electronic devices.

Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process

In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation. The size of DCGS, multi finger number and single finger width of ESD verification structures are designed, and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology. Finally, the optimized GGNMOS is verified on the DSP circuit, and its ESD performance is over 3500 V in HBM mode.

Effect of gate length on performance of 5nm node N-channel nano-sheet transistors for analog circuits

In this work, the effect of channel length on the performance of an N-channel Nano-sheet Transistor (NST) for analog circuits has been investigated. A fully-calibrated TCAD platform is used to evaluate the performance of NST devices with channel lengths ranging from 10 nm to 240 nm. The maximum transconductance measured is 0.65 mS for gate length of 24 nm. In addition, the transconductance efficiency ranging from 3 V−1 to 38 V−1 is observed. Intrinsic gain increases from 7.3 to 121.65 as the gate length is varied from 10 nm to 240 nm. For 12 nm gate length, a unit gain frequency of 565 GHz is observed. NST with 24 nm exhibits Gain Frequency Product value of 5.3 THz. The gain-to-power efficiency improvement from 0.048 µA−1 to 2.16 µA−1 is observed. A reversal of relationships of transconductance and other performance parameters with gate length is observed at 24 nm gate length.

Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction

Tunnel field effect transistors (TFETs) have been exhibiting an enticing performance to succeed in metal–oxide–semiconductor technology. However, TFET also possesses several challenges such as low drive current, ambipolarity, and requirement of abrupt doping profiles for the occurrence of band-to-band tunnelling (BTBT) conduction mechanism at the junction. To overcome these challenges, the authors propose a heterojunction doping less tunnel field-effect transistor with an asymmetric double gate (HJ ADG DLTFET). This device employs a low bandgap material at the source region, which increases the BTBT rate at the channel–source interface leading to enhanced drive current while maintaining low off-current. Consequently, an increment of one order for ION (∼1.5 × 10−5 A/µm) compared to the conventional ADG DLTFET has been provided by this device. Additionally, the comparative analysis of the proposed device and conventional one has been performed to reveal the advantages of the proposed structure in terms of transfer characteristics, transconductance, gate-to-drain capacitance, cut-off frequency, gain–bandwidth product, device efficiency, and transconductance frequency product. Moreover, the effect of gate length and drain voltage variations has been analysed for HJ ADG DLTFET concerning the aforementioned characteristics.

Wide-field time-gated SPAD imager for phasor-based FLIM applications

We describe the performance of a new wide area time-gated single-photon avalanche diode (SPAD) array for phasor-FLIM, exploring the effect of gate length, gate number and signal intensity on the measured lifetime accuracy and precision. We conclude that the detector functions essentially as an ideal shot noise limited sensor and is capable of video rate FLIM measurement. The phasor approach used in this work appears ideally suited to handle the large amount of data generated by this type of very large sensor (512 × 512 pixels), even in the case of small number of gates and limited photon budget.

Analysis of Al0.15Ga0.85N/GaN/Al0.15Ga0.85N DH-HEMT for RF and Microwave Frequency Applications

A charge control based analytical model is followed to study the impact of donor-layer doping and gate-length on microwave frequency performance of AlGaN/GaN/AlGaN double heterostructure high electron mobility transistor (DH-HEMT). DH-HEMT is observed to be more sensitive to gate-length and doping variation as compared to single heterostructure high electron mobility transistor (SH-HEMT). The effect of gate-length and doping on various performance parameters, i.e., transconductance, drain conductance, cut-off frequency and maximum oscillation frequency has been analysed. The results so obtained are compared with simulation results and are found to be in good agreement.

Gate Length Effect on Gallium Nitride Based Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor

We have investigated the performance of Gallium Nitride (GaN) based Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Atlas Device Simulation Framework -Silvaco has been used to access Non-Equilibrium Green Function to distinguish the transfer characteristics curve, ON state current (ION), OFF-state current (IOFF), Drain Induced Barrier Lowering (DIBL), Subthreshold Swing, Electron Current Density, Conduction Band Energy and Electric Field. The concept of Solid state device physics on the effect of gate length studied for the next generation logic applications. GaN-based DG MOSFETs shows better performance than Si-based Single gate MOSFETs. The proposed device has drawn the attention over conventional SG-MOSFET due to fas switching performance. The device turn on and turn off voltage is respectively VGS=1V(On state) and VGS-0V(OFF State). To validate our simulation tool and model results, previous research model has been investigated using Silvaco Atlas and the results obtained are compared to the previous results.

Gate length effect on trapping properties in AlGaN/GaN high-electron-mobility transistors

A comparative study was performed to assess the gate length effect on trapping properties in AlGaN/GaN metal-oxide-semiconductor channel high-electron-mobility transistors. Deep level transient spectroscopy and electrical simulations were used to investigate the deep levels response in two devices with the same gate surface area but with gate lengths of 15 and 1 μm. Results reveal that the repartition of equipotential lines depends on the gate length and impacts trapping phenomena. We demonstrated that the concentration of the defects localized beneath the gate electrode and associated with etching induced damage is reduced with a short gate length. Furthermore, for a negative gate voltage, the depletion region is less extended toward the buffer layers with a gate length of 1 μm, meaning that the trapping effects are reduced. Finally, this work indicates that it is better to design transistors with a short gate length to moderate the effect of trapping phenomena.

Effect of Gate Length on the Electrical Characteristics of Nanoelectronic AlGaN/GaN High Electron Mobility Transistors to Fabricate the Biomedical Sensors in Nanoelectronics

Effect of Gate Length on the Electrical Characteristics of Nanoelectronic AlGaN/GaN High Electron Mobility Transistors to Fabricate the Biomedical Sensors in Nanoelectronics

Oxygen desorption kinetics of ZnO nanorod–gated AlGaN/GaN HEMT-based UV photodetectors

In this study, we investigated the effect of gate length and surface area of the ZnO ultraviolet (UV) absorbing structure on the transient characteristics of AlGaN/GaN HEMT based UV photodetectors. The gate-areas (2, 6 and 18 μm lengths with same width of 100 μm) of AlGaN/GaN HEMTs are covered with ZnO thin film and nanorods (NR) separately. The fabricated devices show enhancement in response speed with the reduction of gate length or the increase of ZnO surface area. The best response speed of ∼10 ms response time and ∼190 ms recovery time is measured from the NR-gated device with a gate length of 2 μm. A model for the oxygen desorption kinetics is proposed for the first time which theoretically shows that the response speed is dependent on two key parameters; light absorbing surface area and gate length. From our model analysis, it is shown that predicted response time is a strong function of these two device parameters, and the calculations show a good agreement with the experimental measurements.

Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors

This paper reports a 2D analytical model for the subthreshold current and subthreshold swing (SS) of ion-implanted Double-Gate Junctionless Field Effect Transistors (DG-JLFETs) with a vertical Gaussian-like doping profile. The effects of gate length, straggle parameter, oxide thickness, channel thickness, and peak doping concentration on subthreshold current and subthreshold swing have been demonstrated. The model results are validated with the simulation data obtained by 2-D TCAD ATLASTM device simulator. Finally, the performance of a CMOS inverter using the DG-JLFET device has been investigated through ATLASTM TCAD mixed mode circuit simulations.

Effect of gate‐length downscaling on the analog/RF and linearity performance of InAs‐based nanowire tunnel FET

SummaryIn this paper, the analog/radio frequency (RF) and linearity performance of an InAs‐based nanowire (NW) tunnel field‐effect transistor (TFET) is studied and compared with InAs‐based NW MSFET of identical dimension. InAs‐based NW TFETs shows a great promise for high performance digital application because of its superior subthreshold behavior. Different analog/RF and linearity key figure‐of‐merits like cut‐off frequency (ft) and 1‐dB compression point are extracted and the effect of gate length down scaling on those parameters has been studied. The results reveal that down scaled InAs‐based NW TFET shows a significant improvement in its RF and linearity performance. However, this advantage diminishes in terms of poor analog performance with gate‐length downscaling. This clearly indicates the necessity of a trade‐off between analog and RF performance. Moreover, an in‐depth comparison between InAs‐based NW TFET and conventional MOSFET has also been provided in order to demonstrate the superiority of InAs‐based NW TFET to become a competitive contender by replacing conventional MOSFET for Analog/Mixed signal System‐on‐Chip (SOC) applications. Copyright © 2016 John Wiley & Sons, Ltd.

Effect of gate length on breakdown voltage in AlGaN/GaN high-electron-mobility transistor**Project supported by the National Natural Science Foundation of China (Grant Nos. 61334002, 61106106, and 61204085).

The effects of gate length LG on breakdown voltage VBR are investigated in AlGaN/GaN high-electron-mobility transistors (HEMTs) with LG = 1 μm∼ 20 μm. With the increase of LG, VBR is first increased, and then saturated at LG = 3 μm. For the HEMT with LG = 1 μm, breakdown voltage VBR is 117 V, and it can be enhanced to 148 V for the HEMT with LG = 3 μm. The gate length of 3 μm can alleviate the buffer-leakage-induced impact ionization compared with the gate length of 1 μm, and the suppression of the impact ionization is the reason for improving the breakdown voltage. A similar suppression of the impact ionization exists in the HEMTs with LG > 3 μm. As a result, there is no obvious difference in breakdown voltage among the HEMTs with LG = 3 μm∼20 μm, and their breakdown voltages are in a range of 140 V–156 V.

Analysis of novel transparent gate recessed channel (TGRC) MOSFET for improved analog behaviour

In this paper, a novel device structure called transparent gate recessed channel MOSFET (TGRC-MOSFET) is proposed to alleviate the hot carrier effects for the advanced nanometer process. TGRC-MOSFET involving a recessed channel and incorporates indium tin oxide as a transparent gate. TCAD analysis shows that the performance of TGRC-MOSFET surpasses conventional recessed channel (CRC)-MOSFET in terms of high ION/IOFF ratio and better carrier transport efficiency in comparison to CRC-MOSFET. This simulation divulges the reduction in hot-carrier-effects metrics like electron velocity, electron temperature, potential, and electron mobility. Furthermore, the effect of gate length is observed on the analog behavior of TGRC-MOSFET. All the simulations have been done using DEVEDIT-3D and ATLAS device simulator. The work proposes the novel design for reduced hot carrier and low power switching applications.

Microwave Analysis for Two-Dimensional C-V and Noise Model of AlGaN/GaN MODFET

A new two-dimensional analytical model for the capacitance-voltage and noise characteristics of a AlGaN/GaN MODFET is developed. The two-dimensional electron gas density is calculated as a function of device dimensions. The model includes the spontaneous and polarization effects. The contribution of various capacitances to the performance of the device is shown. The model further predicts the transconductance, drain conductance, and frequency of operation. A high transconductance of 160 mS/mm and a cut-off frequency of 11.6 GHz are obtained for a device of 50 nm gate length. The effect of gate length on the gate length behaviour of the noise coefficientsP,R, andCis also studied. The effect of parasitic source and gate resistance has also been studied to evaluate the minimum noise figure. The excellent agreement with the previously simulated results confirms the validity of the proposed model to optimize the device performance at high frequencies.

Twin Thin-Film Transistor Nonvolatile Memory With an Indium–Gallium–Zinc–Oxide Floating Gate

A polycrystalline silicon (poly-Si) channel twin thin-film transistor (twin-TFT) nonvolatile memory (NVM) device with In-Ga-Zn-Ox (IGZO) as a storage layer is demonstrated. IGZO-FG twin-TFT NVM exhibits a large memory window ΔVth. A VCG at 18 V for 10 ms can achieve 5.6 V of ΔVth. An extrapolation of the memory window to ten years demonstrates that the stored charge still remains 65% of its initial value. Coupling ratio effect and gate length effect are discussed in detail. Such a low-temperature IGZO-FG twin-TFT NVM device is feasible for integration in IGZO-based display circuits for system-on-panel applications.

Effect of Gate Length on Device Performances of AlSb/InAs High Electron Mobility Transistors Fabricated Using BCl3Dry Etching

Effect of Gate Length on Device Performances of AlSb/InAs High Electron Mobility Transistors Fabricated Using BCl₃Dry Etching