Abstract
The monolayer SiAs2 field-effect transistors (FETs) with gate length (L gate) ranging from 1 to 50 nm were investigated by Silvaco-Atlas simulation in which the main parameters of monolayer SiAs2 were obtained by first-principles calculations. Both the p- and n-FET show extremely high on/off current ratio (1014) and low leakage current (10−18 A μm−1), which are independent of gate length within the 15–50 nm range. And monolayer SiAs2 FETs show practically acceptable values of subthreshold slope and drain-induced barrier lowering when L gate ⩾ 30 nm. On the other hand, the p-and n-FETs show highest transconductance (g m) when L gate is between 25 and 35 nm. Our results suggest that the high performance 35 nm gate length monolayer SiAs2 FETs hold great potential for applications in low-dimensional electronic devices.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
