Single Event Upset Effects Research Articles

Quantifying the Impact of Single-Event Upsets on Neural Networks with Uncertainty Analysis

The Convolutional neural networks have gradually penetrated into various fields of social life, in addition to aerospace devices, neural network chips are also indispensable for target recognition and detection, etc. Due to the complex environment in space, neural network chips are extremely easy to be damaged by cosmic rays, so it is urgent to evaluate and enhance the robustness of neural network chips. However, most of the existing researches are monolithic error injection of neural networks and do not build relevant models for quantitative analysis. The goal of this paper is to analyse the effects of single-event upsets (SEUs) induced by the penetration of SRAM storage areas in a quantized neural network chip by energetic particles from space. Firstly, a SEU probability model as well as an uncertainty assessment model are established, and the effect of SEU on the reliability of CNNs is evaluated by fault injection with the upset rate of four chip types. The results of the error injection experiments show that the Virtex-5 type of rollover rate decreases the average accuracy of VGG-16 by 20%, while the other three types of error injection have an impact of about 11% on the accuracy of the neural network. Quantitative experimental results confirm the hypothesis that SEU increases the uncertainty of neural networks. The quantification of these effects contributes to the study of reinforcement of neural network chips.

Three-dimensional numerical simulation of single event upset effect based on 55 nm DICE latch unit

With the development of nanoscale circuit technology, the on-track error rate of digital circuit and the effect of single event upset have become more pronounced. The radiation resistance research on DICE SRAM or DICE flip-flop device has been carried out extensively, including 65 nm, 90 nm, and 130 nm. However, the research on 55 nm DICE latch has not been reported. Using a three-dimensional device model of the 55 nm bulk silicon process established by the simulation tool TCAD, we verify the reinforcement performance of the DICE circuit, and clarify the effects of different incident conditions on DICE circuits. At the same time, we carry out a comparison of anti-SEU performance between NMOS transistor and PMOS transistor in the 55 nm process through comparative simulation experiments and quantitative analysis. The result shows that one of the important factors is the LET value which affects the generation rate of electron-hole pairs. A higher LET value will extend the upset recovery time of device and increase the peak of voltage. In addition, the difference in charge-sharing mechanism between transistors leads to the recovery time of PMOS higher than that of NMOS. As the angle of incidence increases, the charge-sharing mechanism between adjacent devices is enhanced, and electron-hole pairs ionized in sensitive regions increase. Due to the difference in charge mobility, the sensitivity of the angle of incidence of Nhit in DICE is much greater than that of Phit. Therefore, strict tilt angle incident test evaluation is required for DICE device before practical application. Finally, the large distance between adjacent MOS tubes will weaken the charge-sharing mechanism and reduce the charge collection of adjacent MOS tubes. Simulation result shows that the distance between the MOS transistors in the 55 nm process cannot be less than 1.2 μm. The relevant simulation results can provide a theoretical basis and data for supporting the study of the physical mechanism of SEU and reinforcement technology, thereby promoting the application of memory devices to the aerospace field.

Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories

Low Density Parity Check (LDPC) codes are used in 5G systems for traffic channels due to their excellent error correction capability for long sequences, and the Min-Sum algorithm is widely applied in practical implementations of LDPC decoders due to its low complexity. If the decoder is implemented on a SRAM-based field-programmable gate array (SRAM-FPGA), the radiation-induced single-event upsets (SEUs) can affect the operation of the LDPC decoder by corrupting the configuration memory, which can change the circuit functionality and will not be corrected unless the FPGA is reconfigured. Therefore, protection of LDPC decoders with low overhead is an important problem, especially for resource-limited on-board space systems. In this paper, an efficient Duplicate With Comparison (DWC) protection scheme is proposed based on the different distribution of the parity check sum of the LDPC decoder in the error-free case and the faulty case. In particular, the check sum accumulation number and threshold are optimized to achieve high detection probability with short delay. FPGA based implementation and hardware fault injection experiments are conducted to evaluate the performance of the proposed schemes. Experimental results show that, the effect of SEUs on the LDPC decoder can be completely eliminated by the proposed scheme with 2 times computational overhead and 1.69 times power consumption overhead compared to the unprotected decoder.

Investigation of Single-Event Upset in Graphene Nano-Ribbon FET SRAM Cell.

In recent years, graphene has received so much attention because of its superlative properties and its potential to revolutionize electronics, especially in VLSI. This study analyzes the effect of single-event upset (SEU) in an SRAM cell, which employs a metal-oxide semiconductor type graphene nano-ribbon field effect transistor (MOS-GNRFET) and compares the results with another SRAM cell designed using a PTM 10 nm FinFET node. Our simulations show that there is a change in the data stored in the SRAM after a heavy ion strike. However, it recovers from radiation effects after 0.46 ns for GNRFET and 0.51 ns for FinFET. Since the degradation observed in Q and Qb of GNRFET SRAM are 2.7X and 2.16X as compared to PTM nano-MOSFET, we can conclude that GNRFET is less robust to single effect upset. In addition, the stability of SRAM is improved by increasing the supply voltage VDD.

Simulation of heavy ion irradiation effect on 3D MOSFET

Single event upset effect is an important factor that causes performance degradation and functional failure of aerospace equipment components in space radiation environment. When high-energy particles incident on semiconductor devices in working state, they will induce functional errors of devices and even cause permanent damage. Based on the finite element method, the three-dimensional simulation of Metal-oxide-semiconductor field-effect transistor (MOSFET) is carried out. The single event upset effect of MOSFET under heavy ion irradiation and the influence of heavy ion irradiation on transient drain current are investigated. The results show that the transient drain current of MOSFET devices will increase rapidly when heavy ions are incident, and then the logic state of the devices will change. With the increase in linear energy transfer density, the peak value of the transient drain current pulse increases and the pulse width decreases. With the increase in the incident angle, the peak value of the pulse first increases and then decreases. The maximum value is obtained when the incident angle is vertical, the pulse width first decreases and then increases, and the minimum value is obtained when the incident angle is vertical. With the increase in MOSFET size, the difference of transient drain current formed by symmetrical heavy ion incidence is becoming smaller and smaller. When the incident track is completely in the drain region, the simulation results are the same.

Bootstrapped Driver and the Single-Event-Upset Effect

As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver’s ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumed. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single-event upsets (SEU), which are known to affect DSM circuits working under low voltages. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles.

Measurements of Single Event Upset in ATLAS IBL

Effects of Single Event Upsets (SEU) and Single Event Transients (SET) are studied in the FE-I4B chip of the innermost layer of the ATLAS pixel system. SEU/SET affect the FE-I4B Global Registers as well as the settings for the individual pixels, causing, among other things, occupancy losses, drops in the low voltage currents, noisy pixels, and silent pixels. Quantitative data analysis and simulations indicate that SET dominate over SEU on the load line of the memory. Operational issues and mitigation techniques are presented.

An Approach to Emulate and Validate the Effects of Single Event Upsets using the PREDICT FUTRE Hardware Integrated Framework

Due to the advances in electronics design automation industry, worldwide, the integrated approach to model and emulate the single event effects due to cosmic radiation, in particular single event upsets or single event transients is gaining momentum. As of now, no integrated methodology to inject the fault in parallel to functional test vectors or to estimate the effects of radiation for a selected function in system on chip at design phase exists. In this paper, a framework, PRogrammable single Event effects Demonstrator for dIgital Chip Technologies (PREDICT) failure assessment for radiation effects is developed using a hardware platform and aided by genetic algorithms addressing all the above challenges. A case study is carried out to evaluate the frameworks capability to emulate the effects of radiation using the co-processor as design under test (DUT) function. Using the ML605 and Virtex-6 evaluation board for single and three particle simulations with the layered atmospheric conditions, the proposed framework consumes approximately 100 min and 300 min, respectively; it consumes 600 min for 3 particle random atmospheric conditions, using the 64 GB RAM, 64-bit operating system with 3.1 GHz processor based workstation. The framework output transforms the 4 MeVcm2/mg linear energy transfer to a single event transient pulse width of 2 μs with 105 amplification factor for visualisation, which matches well with the existing experimental results data. Using the framework, the effects of radiation for the co-processing module are estimated during the design phase and the success rate of the DUT is found to be 48 per cent.

Fault-tolerant technology based on FPGA: A Research of LogiCORE™ IP Soft Error Mitigation Controller

In a radiation environment, compared with ASIC and FPGA based on anti-fuse structure, SRAM FPGA is more susceptible to single particle effect, in particular, the effect of single-event upset (SEU). How to improve the equipment anti-single particle over conversion reliability has become a key problem to be considered in the design of SRAM FPGA system. Xilinx provides soft error mitigation SEM IP cores that perform SEU detection, correction, and classification. As part of the SEU detection function, the SEM IP core uses ICAP and ECC primitives for clock control and observing the CRC circuit reading back. As far as SEU correction is concerned, the IP core performs the necessity through the built-in ECC function and the operation to locate and correct SEU errors. For the SEU classification, the IP core uses the Xilinx-Essential-Bit technology further to improve system reliability. Through the in-depth analysis of SEM, in this paper, soft error mitigation SEM controller IP core of Xilinx was used to build a verification and test platform based on Zynq-7000 SoC ZC702 in order to simulate the influence of cosmic irradiation on SRAM FPGA. On the basis of completing the functional verification of SEM IP core, we also put forward some improvement ideas based on the experimental results.

Characterization of various FinFET based 6T SRAM cell configurations in light of radiation effect

The microelectronics circuits used in the aerospace applications work in an extremely radiated environment, causing a large possibility of a single event upset (SEU). Static random access memory (SRAM) is the most susceptible of these circuits as it occupies a significant area of the recent System-on-Chip (SoC) and also frequently store important data. Therefore, retaining data integrity with regards to SEUs has become a primary requirement of SRAM bit-cell design. Use of FinFET devices in the SRAM cell can offer higher resistance against radiation compared to the CMOS counterparts. In this work, using TCAD simulations, we have analysed effect of SEU on three different FinFET based 6T bit-cell configurations, in which number of fins in the access and pull-down transistors are different. We have analysed the effect of SEU at an angle of 90° and 60°.

Single event upset on static random access memory devices due to spallation, reactor, and monoenergetic neutrons**Project supported by the National Natural Science Foundation of China (Grant Nos. 11690040 and 11690043) and the Foundation of State Key Laboratory of China (Grant Nos. SKLIPR1801Z and 6142802180304).

This paper presents new neutron-induced single event upset (SEU) data on the SRAM devices with the technology nodes from 40 nm to 500 nm due to spallation, reactor, and monoenergetic neutrons. The SEU effect is investigated as a function of incident neutron energy spectrum, technology node, byte pattern and neutron fluence rate. The experimental data show that the SEU effect mainly depends on the incident neutron spectrum and the technology node, and the SEU sensitivity induced by low-energy neutrons significantly increases with the technology downscaling. Monte–Carlo simulations of nuclear interactions with device architecture are utilized for comparing with the experimental results. This simulation approach allows us to investigate the key parameters of the SEU sensitivity, which are determined by the technology node and supply voltage. The simulation shows that the high-energy neutrons have more nuclear reaction channels to generate more secondary particles which lead to the significant enhancement of the SEU cross-sections, and thus revealing the physical mechanism for SEU sensitivity to the incident neutron spectrum.

Design of an anti‐irradiation beam‐steering unit based on ASIC circuit

There are a large number of high-energy particles in the space. These high-energy particles induce a single-event upset effect on DSP, FPGA, and other programmable digital controllers inside the beam-steering unit, which can produce unpredictable and erroneous influences, thereby reducing the reliability of space-borne-phased array radars. In order to solve the above problems, this study presents a design of beam-steering unit based on a kind of application-specific integrated circuit (ASIC). By using the advantages of ASIC circuits such as strong radiation resistance, high integration, and low power consumption, this solution adopts an anti-irradiation ASIC chip as a controller, and anti-irradiation RS422 transceivers are used to complete interface conversion for receiving data and transmitting data. The beam refreshing and telemetry functions between the beam control computer and the 24 microwave modules are realised finally. The test result shows that the phase distribution time is <30 μs when the clock is 3.125 MHz, and the falling edge of sampling pulse is located at half the length of a data symbol, ensuring data hold time long enough to sample correctly.

RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers

This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 μ m CMOS technology. In CMOS devices, the effect of a high energy particle impact can be modeled by a current pulse connected to the drain of the transistors. The effects of SET (single event transient) and SEU (single event upset) were analyzed connecting current pulses to the drains of all the transistors and analyzing the amplitude variations and phase shifts obtained at the output nodes. Following this procedure, the most sensitive circuits were detected. This paper proposes a combination of radiation hardening-by-design techniques (RHBD) such as resistor–capacitor (RC) filtering or local circuit-redundancy to mitigate the effects of radiation. The proposed modifications make the frequency synthesizer more robust against radiation.

Characterization and Mitigation of Single-Event Transients in Xilinx 45-nm SRAM-Based FPGA

This paper presents a new approach for analyzing the effect of single-event transient (SET) in SRAM-based field-programmable gate array (FPGA) devices, which are widely used in the space environment. New SET characterizing and mitigation techniques, including continuous monitoring and controlling of the test, are proposed to ensure proper operation of the device under test. This is vital for verifying the proper functioning of the design and performing online reconfiguration if required, since the effect of a single-event upset (SEU) on the device configuration bits may disrupt the SET detection and mitigation design. While many studies focus on SEU, latch-up, and cumulative radiation [total ionizing dose (TID)] effects on SRAM-based FPGAs, only a few published works refer to the SET effect. Moreover, in contrast to previous SET studies, this paper presents a quantitative assessment for SET probability under the real radiation environment and provides cross-sectional analysis for both SET and SEU effects at low linear energy transfers (LETs) (up to 0.925 MeV $\cdot$ cm2/mg). The SET experiments have been carried out at UCL Cyclotron (Belgium) accelerator using heavy ions and under alpha source irradiation. Experimental results indicate that SET examinations on SRAM-based FPGAs should be performed only at low LETs due to the high SEU rate compared to the SET rate. Several kinds of filters have been implemented and proposed for SET mitigation demonstrating a significant reduction of the SET transient effects. The proposed methodology may provide a basic model for future research studies on SET radiation effects on SRAM-based FPGAs, and assisting in selecting an immune FPGA-based platform for satellites applications.

An Adjustable and Fast Error Repair Scrubbing Method Based on Xilinx Essential Bits Technology for SRAM-Based FPGA

Field programmable gate array (FPGA) is becoming more valuable for space applications because of its large density, high performance, reduced development cost and flexible programmability. In particular, static random access memory (SRAM) based FPGA is very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. However, SRAM-based FPGA contains a large number of memory cells which are very sensitive to single event upset (SEU). SEU in SRAM-based FPGA may result in a functional error unless the FPGA is reconfigured. In this paper, we propose a fast adjustable scrubbing method based on Xilinx essential bits technology to mitigate the effect of SEU for SRAM-based FPGA. The whole scrubbing flow contains two sub-flows: partial scrubbing and entire scrubbing. This scrubbing method not only increases the speed of repairing an error for user design, but also ensures the reliability of whole FPGA design. We test the proposed scrubbing method through fault injection. Finally, we show the error repair speeds of user designs for different repeat cycles of partial scrubbing and summarize the optimized repeat cycles of partial scrubbing.

Strategies for Removing Common Mode Failures From TMR Designs Deployed on SRAM FPGAs

Triple modular redundancy (TMR) with repair has proven to be an effective strategy for mitigating the effects of single-event upsets within the configuration memory of static random access memory field-programmable gate arrays. Applying TMR to the design successfully reduces the design's neutron cross section by 80×. The effectiveness of TMR, however, is limited by the presence of single bits in the configuration memory which cause more than one TMR domain to fail simultaneously. We present three strategies to mitigate against these failures and improve the effectiveness of TMR: incremental routing, incremental placement, and striping. These techniques were tested using both fault injection and a wide spectrum neutron beam with the best technique offering a 400× reduction to the design's sensitive neutron cross section. An analysis from the radiation test shows that no single bits caused failure and that multicell upsets were the main cause of failure for these mitigation strategies.

Analysis of Temporal Masking Effects on Master- and Slave-Type Flip-Flop SEUs and Related Applications

Analysis of temporal masking effects of single-event upsets (SEUs) on master–slave flip-flops (FFs) is provided, considering the difference of SEU cross sections between master and slave latches. An improved model of temporal masking effects of SEUs in master–slave FFs is proposed and demonstrated through alpha-particle single-event effect (SEE) experiments. Based on the improved model, an effective and accurate methodology to quantitatively evaluate single-event transient and SEU-induced error cross sections of FF chains is proposed. Implications of SEE hardening for sequential circuits are discussed.

Soft-error tolerance and energy consumption evaluation of embedded computer with magnetic random access memory in practical systems using computer simulations

We evaluated the soft-error tolerance and energy consumption of an embedded computer with magnetic random access memory (MRAM) using two computer simulators. One is a central processing unit (CPU) simulator of a typical embedded computer system. We simulated the radiation-induced single-event-upset (SEU) probability in a spin-transfer-torque MRAM cell and also the failure rate of a typical embedded computer due to its main memory SEU error. The other is a delay tolerant network (DTN) system simulator. It simulates the power dissipation of wireless sensor network nodes of the system using a revised CPU simulator and a network simulator. We demonstrated that the SEU effect on the embedded computer with 1 Gbit MRAM-based working memory is less than 1 failure in time (FIT). We also demonstrated that the energy consumption of the DTN sensor node with MRAM-based working memory can be reduced to 1/11. These results indicate that MRAM-based working memory enhances the disaster tolerance of embedded computers.

Towards an efficient SEU effects emulation on SRAM-based FPGAs

A novel fault injection approach, reproducing results obtained from radiation ground testing while studying the Single Event Upset (SEU) effects on SRAM-based Field Programmable Gate Arrays (FPGAs), is presented. This approach can take into account the relative sensitivity difference between configuration bits set to ‘0’ and those set to ‘1’. According to irradiation experiments conducted under proton beam for a Xilinx Virtex-5 FPGA at the TRIUMF lab, configuration bits set to ‘1’ are approximately twice as sensitive as bits set to ‘0’. This fact was exploited in test sequence generation while performing fault injection experiments, in order to generate more realistic emulation results. The effectiveness of the approach is validated by comparing its results to those obtained with proton radiation tests, for two different ring-oscillator-based experimental setups. It shows that taking this sensitivity into account helps obtain more realistic results while dealing with delays induced by radiation, which justifies considering this relative sensitivity during fault emulation. In fact, comparing the results obtained from the proposed approach to those obtained at TRIUMF gives an absolute relative error of 3.1 and 14%, respectively, for the first and the second setups, while estimating the error between the latter and results from a conventional random fault injection provides error values of up to 75%. Finally, applying our fault injection approach on a more conventional circuit reveals that taking the relative sensitivity difference into account leads to 2.3 times as many errors detected as with random injection. This last result suggests that not taking the relative sensitivity difference into account during emulation can lead to an underestimation of a design sensitivity to radiation.

Memory State Transient Analysis (MSTA): A New Soft Error Rate Measurement Method for CMOS Memory Elements Based on Stochastic Analysis

We analyze the evolution of SRAM memory logic contents under irradiation by defining the memory state as the number of cells storing a given logic value (i.e. number of cells storing a logic-1). We find that the memory state evolution under irradiation follows an Ehrenfest urn model due to the constant effect of single event upsets, and that in large memories it can be associated to an Ornstein-Uhlenbeck process. Memory state transient analysis has been applied to determine the device Soft error rate for an SRAM fabricated in a 65 nm commercial CMOS process obtaining a very good correlation. Furthermore, our analysis shows that the technique is applicable to systems composed by various dissimilar memory components, providing–under certain circumstances–the specific Soft Error Rate of each component.