Fault-tolerant technology based on FPGA: A Research of LogiCORE™ IP Soft Error Mitigation Controller

Abstract

In a radiation environment, compared with ASIC and FPGA based on anti-fuse structure, SRAM FPGA is more susceptible to single particle effect, in particular, the effect of single-event upset (SEU). How to improve the equipment anti-single particle over conversion reliability has become a key problem to be considered in the design of SRAM FPGA system. Xilinx provides soft error mitigation SEM IP cores that perform SEU detection, correction, and classification. As part of the SEU detection function, the SEM IP core uses ICAP and ECC primitives for clock control and observing the CRC circuit reading back. As far as SEU correction is concerned, the IP core performs the necessity through the built-in ECC function and the operation to locate and correct SEU errors. For the SEU classification, the IP core uses the Xilinx-Essential-Bit technology further to improve system reliability. Through the in-depth analysis of SEM, in this paper, soft error mitigation SEM controller IP core of Xilinx was used to build a verification and test platform based on Zynq-7000 SoC ZC702 in order to simulate the influence of cosmic irradiation on SRAM FPGA. On the basis of completing the functional verification of SEM IP core, we also put forward some improvement ideas based on the experimental results.