Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders

Abstract

This paper analyzes the effects of single event upsets (SEUs) on the user memory of a Viterbi decoder implemented on an SRAM based FPGA. First, an FPGA Viterbi decoder implementation is used to study the structures that are mapped to user memory. Then, the SEUs tolerance capability for each of those structures is analyzed theoretically. Finally, fault injection experiments are performed to verify the analysis. Both the analysis and experiment results show that most of SEUs on user memories can be tolerated by the Viterbi decoder, and the lower bit error rate, the better the fault tolerance of the decoder. Even for high bit error rate that exceeds the error correction limit of the decoder, over 95% of SEUs on user memories can be tolerated. The SEUs tolerance analysis and the results will be used to implement a selective hardening of the decoder in the future.